Patents by Inventor Tzu-Yang YEN

Tzu-Yang YEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180321701
    Abstract: A current balance circuit is used in a multiphase converter, and the multiphase converter includes power stage circuits, the current balance circuit and a control circuit. The current balance circuit includes detection units, a calculation circuit and error amplifiers. Detection units obtain the output power information of their corresponding power stage circuits. After each error amplifier compares the obtained output power information with the average of all output power information, it amplifies differences between the output power information and the average of all output power information and converts the amplified differences to current information, such that the control circuit adjusts currents provided by the power stage circuits according to the current information from the error amplifiers to balance the currents provided by the power stage circuits.
    Type: Application
    Filed: July 7, 2017
    Publication date: November 8, 2018
    Inventors: CHIH-YUAN CHEN, TZU-YANG YEN
  • Patent number: 9847720
    Abstract: Provided herein are a single-inductor dual-output (SIDO) power converter operable in a discontinuous conduction mode and a control method thereof. The SIDO power converter is operable to switch between a boost mode and a buck-boost mode. The SIDO power converter dynamically adjusts output timings of clock signals with respect to the loads according to a load difference therebetween to lower the power consumption with a light load when the inductor current is zero to achieve optimal power distribution.
    Type: Grant
    Filed: November 29, 2015
    Date of Patent: December 19, 2017
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Chih-Yuan Chen, Tzu-Yang Yen
  • Patent number: 9651959
    Abstract: The present disclosure illustrates a single-inductor dual-output (SIDO) power converter for hysteresis current control mode and a control method thereof. In the SIDO power converter provided by the instant disclosure, a detecting circuit, connected to the upper bridge transistor, determines whether the inductive current reaches the upper limit threshold or the lower limit threshold, and further drives a control circuit to turn on or off the corresponding upper bridge transistor and/or the lower bridge transistor, so as to simplify the operation of the hysteresis current control mode.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: May 16, 2017
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Chih-Yuan Chen, Tzu-Yang Yen
  • Patent number: 9564809
    Abstract: A zero current detecting circuit is disclosed. The zero current detecting circuit includes a first zero current comparator for determining current variation on an inductor of a synchronous switching power converter so as to output a zero current signal to turn off a down-bridge transistor of the synchronous power converter; a second zero current comparator for determining whether the first zero current comparator turns off the down-bridge transistor too early or too late and outputting a comparison result; a counter coupled to the second zero current comparator for ascending or descending a control bit according to the comparison result, and an adjustable delay unit coupled to the first zero current comparator and the counter for adjusting a delay time according to the control bit, and delaying and outputting the zero current signal according to the delay time, to compensate a negative offset voltage by delay.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: February 7, 2017
    Assignee: Anpec Electronics Corporation
    Inventors: Chih-Yuan Chen, Tzu-Yang Yen
  • Publication number: 20170033689
    Abstract: Provided herein are a single-inductor dual-output (SIDO) power converter operable in a discontinuous conduction mode and a control method thereof. The SIDO power converter is operable to switch between a boost mode and a buck-boost mode. The SIDO power converter dynamically adjusts output timings of clock signals with respect to the loads according to a load difference therebetween to lower the power consumption with a light load when the inductor current is zero to achieve optimal power distribution.
    Type: Application
    Filed: November 29, 2015
    Publication date: February 2, 2017
    Inventors: CHIH-YUAN CHEN, TZU-YANG YEN
  • Publication number: 20170023959
    Abstract: The present disclosure illustrates a single-inductor dual-output power converter for hysteresis current control mode and a control method thereof. The SIDO power converter comprises an upper bridge transistor, a lower bridge transistor, an inductor, an error amplifying circuit, a detecting circuit and a control circuit. The error amplifying circuit outputs a first loading signal and a second loading signal according to a first output voltage and a second output voltage, respectively. The detecting circuit is coupled to the upper bridge transistor. The detecting circuit detects whether a detecting value is between an upper limit threshold and a lower limit threshold, in order to inform the control circuit switching off the upper bridge transistor and/or the lower bridge transistor.
    Type: Application
    Filed: October 23, 2015
    Publication date: January 26, 2017
    Inventors: CHIH-YUAN CHEN, TZU-YANG YEN
  • Patent number: 9543826
    Abstract: An audible noise avoiding circuit and a DC-DC boost converter for a DC-DC boost converter are provided. The audible noise avoiding circuit comprises a timing controller and a linear regulator. The timing controller discharges a timing capacitor to a low voltage according to switching of the DC-DC boost converter. A sink output stage of the liner regulator is coupled to the output voltage node. When the voltage of the timing capacitor is higher than a threshold voltage, the compensation unit compensates the output of the operational amplifier for gradually turning on the sink output stage in order to gradually reduce the voltage of the output voltage node. A predetermined charging time interval is defined by the time interval of charging the timing capacitor from the low voltage to the threshold voltage, the reciprocal of the predetermined time interval is a frequency in the ultrasonic wave frequency range.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: January 10, 2017
    Assignee: Anpec Electronics Corporation
    Inventors: Chih-Yuan Chen, Tzu-Yang Yen
  • Publication number: 20160308441
    Abstract: A zero current detecting circuit is disclosed. The zero current detecting circuit includes a first zero current comparator for determining current variation on an inductor of a synchronous switching power converter so as to output a zero current signal to turn off a down-bridge transistor of the synchronous power converter; a second zero current comparator for determining whether the first zero current comparator turns off the down-bridge transistor too early or too late and outputting a comparison result; a counter coupled to the second zero current comparator for ascending or descending a control bit according to the comparison result, and an adjustable delay unit coupled to the first zero current comparator and the counter for adjusting a delay time according to the control bit, and delaying and outputting the zero current signal according to the delay time, to compensate a negative offset voltage by delay.
    Type: Application
    Filed: September 1, 2015
    Publication date: October 20, 2016
    Inventors: Chih-Yuan Chen, Tzu-Yang Yen
  • Publication number: 20160056712
    Abstract: An audible noise avoiding circuit and a DC-DC boost converter for a DC-DC boost converter are provided. The audible noise avoiding circuit comprises a timing controller and a linear regulator. The timing controller discharges a timing capacitor to a low voltage according to switching of the DC-DC boost converter. A sink output stage of the liner regulator is coupled to the output voltage node. When the voltage of the timing capacitor is higher than a threshold voltage, the compensation unit compensates the output of the operational amplifier for gradually turning on the sink output stage in order to gradually reduce the voltage of the output voltage node. A predetermined charging time interval is defined by the time interval of charging the timing capacitor from the low voltage to the threshold voltage, the reciprocal of the predetermined time interval is a frequency in the ultrasonic wave frequency range.
    Type: Application
    Filed: November 2, 2015
    Publication date: February 25, 2016
    Inventors: CHIH-YUAN CHEN, TZU-YANG YEN
  • Publication number: 20140375285
    Abstract: The present disclosure provides a DC-DC boost converter operating in a pulse frequency modulation mode. The DC-DC boost converter includes an inductor, a first switch, a capacitor, a second switch and a control circuit. The inductor is coupled between an input voltage node and a phase node. The first switch is coupled between the phase node and an output voltage node. The capacitor is coupled between the output voltage node and a ground. The second switch is coupled between the phase node and the ground. The control circuit controls the conducting status of the first switch and the second switch. The control circuit detects whether the voltage at the phase node is changed. When the voltage at the phase node is not changed during a predetermined time interval, the control circuit turns on the first switch. Therefore, the noise with frequency could be hear by human is avoided.
    Type: Application
    Filed: August 16, 2013
    Publication date: December 25, 2014
    Applicant: ANPEC ELECTRONICS CORPORATION
    Inventors: CHIH-YUAN CHEN, TZU-YANG YEN
  • Patent number: 8896283
    Abstract: The synchronous switching power converter comprises an inductor; a down bridge transistor; and a zero current detection circuit comprising a zero current comparator for receiving a fixed comparing level at a negative input end for comparison to change state of a comparing result; a delay unit, for delaying the comparing result to change state of a turn off signal according to a compensation voltage, to turn off the down bridge transistor when determining current on the inductor is zero; a transient state adjusting circuit for indicating a transient period when detecting state of the turn off signal is changed; and an integrator for integrating the compensation voltage by analog manner to adjust value of the compensation voltage and providing to the delay unit within the transient period; wherein the zero current comparator determines the integrator to integrate positively or negatively within the transient period.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: November 25, 2014
    Assignee: Anpec Electronics Corporation
    Inventors: Chih-Yuan Chen, Tzu-Yang Yen
  • Patent number: 8723497
    Abstract: A constant-on-time generation circuit for generating a turn-on signal to a buck is disclosed. The constant-on-time generation circuit includes a capacitor, a current source, a second resistor, an inverter, a transistor coupled to the inverter for generating a set turn-on signal according to a first front-end driver signal of the buck converter, a comparator including a negative input terminal coupled to a reference voltage, a positive input terminal coupled to the second resistor and the current source, and an output terminal, for comparing the reference voltage with the set turn-on signal to output a comparison result, and an SR-latch for outputting a turn-on signal to a driver stage circuit of the buck converter according to a trigger signal of the buck converter and the comparison result.
    Type: Grant
    Filed: September 3, 2012
    Date of Patent: May 13, 2014
    Assignee: Anpec Electronics Corporation
    Inventors: Tzu-Yang Yen, Chih-Yuan Chen
  • Publication number: 20140111168
    Abstract: The synchronous switching power converter comprises an inductor; a down bridge transistor; and a zero current detection circuit comprising a zero current comparator for receiving a fixed comparing level at a negative input end for comparison to change state of a comparing result; a delay unit, for delaying the comparing result to change state of a turn off signal according to a compensation voltage, to turn off the down bridge transistor when determining current on the inductor is zero; a transient state adjusting circuit for indicating a transient period when detecting state of the turn off signal is changed; and an integrator for integrating the compensation voltage by analog manner to adjust value of the compensation voltage and providing to the delay unit within the transient period; wherein the zero current comparator determines the integrator to integrate positively or negatively within the transient period.
    Type: Application
    Filed: January 10, 2014
    Publication date: April 24, 2014
    Applicant: ANPEC ELECTRONICS CORPORATION
    Inventors: Chih-Yuan Chen, Tzu-Yang Yen
  • Publication number: 20130257403
    Abstract: A constant-on-time generation circuit for generating a turn-on signal to a buck is disclosed. The constant-on-time generation circuit includes a capacitor, a current source, a second resistor, an inverter, a transistor coupled to the inverter for generating a set turn-on signal according to a first front-end driver signal of the buck converter, a comparator including a negative input terminal coupled to a reference voltage, a positive input terminal coupled to the second resistor and the current source, and an output terminal, for comparing the reference voltage with the set turn-on signal to output a comparison result, and an SR-latch for outputting a turn-on signal to a driver stage circuit of the buck converter according to a trigger signal of the buck converter and the comparison result.
    Type: Application
    Filed: September 3, 2012
    Publication date: October 3, 2013
    Applicant: ANPEC ELECTRONICS CORPORATION
    Inventors: Tzu-Yang Yen, Chih-Yuan Chen
  • Patent number: 8441238
    Abstract: A zero current detecting circuit is disclosed. The zero current detecting circuit includes a first zero current comparator for determining current variation on an inductor of a synchronous switching power converter so as to accordingly turn off a down-bridge transistor of the synchronous power converter; a second zero current comparator for determining whether the first zero current comparator turns off the down-bridge transistor too early or too late and outputting a comparison result, and a counter coupled to the second zero current comparator for ascending or descending a control bit according to the comparison result.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: May 14, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Ke-Horng Chen, Tzu-Yang Yen
  • Publication number: 20120235653
    Abstract: A zero current detecting circuit is disclosed. The zero current detecting circuit includes a first zero current comparator for determining current variation on an inductor of a synchronous switching power converter so as to accordingly turn off a down-bridge transistor of the synchronous power converter; a second zero current comparator for determining whether the first zero current comparator turns off the down-bridge transistor too early or too late and outputting a comparison result, and a counter coupled to the second zero current comparator for ascending or descending a control bit according to the comparison result.
    Type: Application
    Filed: August 8, 2011
    Publication date: September 20, 2012
    Inventors: Ke-Horng Chen, Tzu-Yang Yen
  • Publication number: 20120176104
    Abstract: Zero current detecting circuit includes a zero current comparator for determining current variation on an inductor of a synchronous switching power converter so as to accordingly turn off a down bridge transistor of the synchronous power converter; an integrator for executing integration to the signal on an input end of the zero current comparator within a transient period after the down bridge transistor is turned off, for eliminating the effect from the offset voltage of the zero current comparator; and an integration controller for determining if the down bridge transistor is turned off too early or too late so as to control the integrator to positively or negatively integrate.
    Type: Application
    Filed: March 8, 2011
    Publication date: July 12, 2012
    Inventors: Chih-Yuan CHEN, Tzu-Yang YEN