Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.

Abstract: A manufacturing method of a package-on-package structure includes forming a first package structure and staking a second package structure over the first package structure. The first package structure is formed by at least the following steps. A first redistribution structure is provided. Conductive structures are formed on the first redistribution structure. A die is placed between the conductive structures. The die and the conductive structures are encapsulated by an encapsulant. The encapsulant is planarized such that an entirety of a top surface of the encapsulant is coplanar with an entirety of top surfaces of the conductive structures. A second redistribution structure is formed on the encapsulant. The second redistribution structure includes a conductive pattern layer that is in physical contact with the top surfaces of the encapsulant and the conductive structures. An entire bottom surface of the conductive pattern layer is located at a same level height.

Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction. The gate structure includes a first portion and a second portion separated by the gate isolation structure and the dielectric fin. The first portion of the gate structure presents a first beak profile and the second portion of the gate structure presents a second beak profile. The first and second beak profiles point toward each other.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor device including a shallow trench isolation (STI) structure disposed between a first side and a second side of the semiconductor substrate. An intermetal dielectric structure comprising a first metal interconnect is on the second side. A first etching process is performed to form a first trench extending from the first side of the semiconductor substrate to the STI structure. An etch stop layer is deposited on the first side. A dielectric material is deposited into the first trench to form a dielectric spacer. A second trench is etched during a second etching process. The second trench is aligned with the first trench and extends through the STI structure to the first metal interconnect. A conductive material is deposited into the second trench to form a contact pad that contacts the first metal interconnect.

Abstract: A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.

Abstract: A semiconductor epitaxy structure includes a silicon carbide substrate, a nucleation layer, a gallium nitride buffer layer, and a stacked structure. The nucleation layer is formed on the silicon carbide substrate, the gallium nitride buffer layer is disposed on the nucleation layer, and the stacked structure is formed between the nucleation layer and the gallium nitride buffer layer. The stacked structure includes: a plurality of silicon nitride (SiNx) layers and a plurality of aluminum gallium nitride (AlxGa1-xN) layers alternately stacked, wherein the first layer of the plurality of silicon nitride layers is in direct contact with the nucleation layer.

Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.

Abstract: A metalens including a transparent substrate and lenses is provided. The lenses are located on the transparent substrate. Each of the lenses includes first columnar microstructures continuously arranged along a first direction and second columnar microstructures continuously arranged along a second direction. A pitch of the first columnar microstructure is different from a pitch of the second columnar microstructure.

Abstract: A chiral molecule detector includes a light source, a photodetector, and a carrier. The carrier is configured to reflect at least part of light emitted by the light source to the photodetector. The carrier includes a substrate and a metal reflective layer. An upper surface of the substrate has a periodic hole array containing multiple holes. The metal reflective layer is located on the upper surface of the substrate, and covers a sidewall of the hole and a bottom surface of the hole.

Abstract: A method of manufacturing a high electron mobility transistor (HEMT) structure is disclosed. By controlling a passivation layer and a barrier layer to uninterruptedly grow in the same growth chamber, defects of the passivation layer generated in the growth process due to a drastic change in temperature, pressure, or atmosphere or degrading a quality of an interface between the passivation layer and the barrier layer could be avoided, thereby providing the passivation layer with a good quality and the interface between the passivation layer and the barrier layer with a good quality, so that the objective of improving the performance of the HEMT structure could be achieved.

Abstract: A semiconductor epitaxy structure includes a silicon carbide substrate, a nucleation layer, a gallium nitride buffer layer, and a stacked structure. The nucleation layer is formed on the silicon carbide substrate, the gallium nitride buffer layer is disposed on the nucleation layer, and the stacked structure is formed between the nucleation layer and the gallium nitride buffer layer. The stacked structure includes: a plurality of silicon nitride (SiNx) layers and a plurality of aluminum gallium nitride (AlxGa1-xN) layers alternately stacked, wherein the first layer of the plurality of silicon nitride layers is in direct contact with the nucleation layer.

Abstract: A semiconductor structure includes a substrate, a first nitride layer, a second nitride layer, a third nitride layer, and a polarity inversion layer. The first nitride layer is formed on the substrate, and the polarity inversion layer formed at a surface of the first nitride layer converts a non-metallic polar surface of the first nitride layer into a metallic polar surface of the polarity inversion layer. The second nitride layer is formed on the polarity inversion layer. The third nitride layer is formed on the second nitride layer.

Abstract: An epitaxial structure and a semiconductor device are provided in which the epitaxial structure includes at least a SiC substrate, a nucleation layer, and a GaN layer. The nucleation layer is formed on the SiC substrate. The material of the nucleation layer is aluminum gallium nitride doped with a dopant, the Al content in the nucleation layer changes from high to low in the thickness direction, the lattice constant of the nucleation layer is between 3.08 ? and 3.21 ?, and the doping concentration of the nucleation layer changes from high to low in the thickness direction. The GaN layer is formed on the nucleation layer.

Abstract: An epitaxial structure includes a substrate, a buffer layer, a channel layer, a barrier layer, a diffusion barrier layer, and a P-type gallium nitride layer sequentially stacked from bottom to top. The P-type gallium nitride layer has a first lattice constant. The diffusion barrier layer includes a chemical composition of Inx1Aly1Gaz1N, where x1+y1+z1=1, 0?x1?0.3, 0?y1?1.0, and 0?z1?1.0. The chemical composition of the diffusion barrier layer has a proportional relationship so that the diffusion barrier layer has a second lattice constant that matches the first lattice constant, and the second lattice constant is between 80% and 120% of the first lattice constant.

Abstract: An epitaxial structure and a semiconductor device are provided in which the epitaxial structure includes at least a SiC substrate, a nucleation layer, and a GaN layer. The nucleation layer is formed on the SiC substrate. The material of the nucleation layer is aluminum gallium nitride doped with a dopant, the Al content in the nucleation layer changes from high to low in the thickness direction, the lattice constant of the nucleation layer is between 3.08 ? and 3.21 ?, and the doping concentration of the nucleation layer changes from high to low in the thickness direction. The GaN layer is formed on the nucleation layer.

Abstract: An epitaxial structure including at least a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a P-type aluminum indium gallium nitride layer is provided. The nucleation layer is formed on the substrate; the buffer layer is formed on the nucleation layer; the channel layer is formed on the buffer layer; the barrier layer is formed on the channel layer; and the P-type aluminum indium gallium nitride layer is formed on the barrier layer. The material of the P-type aluminum indium gallium nitride layer is AlInGaN with a P-type dopant, in which the contents of Al, In and Ga all change stepped-periodically or stepped-periodical-gradually in the thickness direction, and the doping concentration of the P-type dopant changes stepped-periodically or stepped-periodical-gradually in the thickness direction.

Abstract: A manufacturing method of a graphene metal composite material includes the steps of providing metal powder including metal particles, graphene powder including graphene pieces and binder including wax material, wherein each graphene piece includes graphene molecules connected with each other and including six carbon atoms annually connected, and one of the carbon atom of each graphene molecule is bonded with a functional group by an SP3 bond; mixing the powders and the binder into a powder material, wherein the SP3 bond is heated and broken by friction, and the graphene molecules are connected with each other via the broken SP3 bond to wrap the respective metal particles; melting and molding the powder material to form a green part; removing the binder from the green part to form a brown part; and sintering the brown part to form a metal main part embedded a three-dimensional mash formed by the graphene molecules.

Abstract: A depth image processing method and a depth image processing system are provided. The depth image processing method includes: capturing a first image and a second image; performing a feature comparison to acquire a plurality of feature pairs between the first image and the second image, wherein each of the feature pairs includes a feature in the first image and a corresponding feature in the second image; computing disparities of the feature pairs; computing a depth image through the first image and the second image when the disparities of the feature pairs are all smaller than a disparity threshold.

Abstract: A depth image processing method and a depth image processing system are provided. The depth image processing method includes: capturing a first image and a second image; performing a feature comparison to acquire a plurality of feature pairs between the first image and the second image, wherein each of the feature pairs includes a feature in the first image and a corresponding feature in the second image; computing disparities of the feature pairs; computing a depth image through the first image and the second image when the disparities of the feature pairs are all smaller than a disparity threshold.