Abstract: The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.

Abstract: The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.

Abstract: A method for manufacturing an electronic device includes: providing a base layer, wherein the base layer includes a plurality of first dies and a plurality of second dies, and a number of the plurality of first dies is greater than a number of the plurality of second dies; forming a circuit layer on the base layer; and performing an electricity test to confirm whether the circuit layer is electrically connected to one of the plurality of second dies.

Abstract: A manufacturing method of a package structure of an electronic device, including the following steps, is provided. A first seed layer is formed on a carrier plate. A first metal layer is formed on the first seed layer. A first insulating layer is formed on the first metal layer, wherein the first insulating layer exposes a portion of the first metal layer. A first plasma treatment is performed on the first insulating layer and the exposed portion of the first metal layer. After performing the first plasma treatment, the carrier plate formed with the first seed layer, the first metal layer, and the first insulating layer is placed in a microenvironment controlling box. After taking the carrier plate out of the microenvironment controlling box, a second seed layer is formed on the first insulating layer and the exposed portion of the first metal layer.

Abstract: A method for manufacturing a composite layer circuit structure of an electronic device is provided. First, a first conductive layer is formed on a carrier plate. Next, a first photoresist layer is formed on the first conductive layer. The first photoresist layer includes multiple first openings exposing part of the first conductive layer. Next, a first electroplating layer is formed in the first openings. Then, the first photoresist layer is removed. Then, a first insulating layer is formed on the first conductive layer. The first insulating layer includes multiple second openings exposing part of the first electroplating layer. In the above, at least one heat treatment process is performed on the first electroplating layer before the first insulating layer is formed on the first conductive layer. A temperature when performing at least one heat treatment process is higher than or equal to 40° C. and lower than or equal to 300° C.