Abstract: Methods and apparatus of video coding using sub-block based affine mode are disclosed. According to this method, control-point motion vectors (MVs) associated with the affine mode are determined for a block. A sub-block MV is derived for a target sub-block of the block from the control-point MVs for the block. A prediction offset is determined for a target pixel of the target sub-block using information comprising a pixel MV offset from the sub-block MV for the target pixel according to Prediction Refinement with Optical Flow (PROF). The target pixel of the target sub-block is encoded or decoded using a modified predictor. The modified prediction is generated by clipping the prediction offset to a target range and combining the clipped prediction offset with an original predictor.

Abstract: A method and apparatus of video coding, where according to one method, input data related to a current block in a current picture are received at a video encoder side or compressed data comprising the current block are received at a video decoder side. A first syntax at a high level in a video bitstream regarding residual coding type is signaled at the encoder side or parsed at the decoder side. A target coding mode is determined for the current block based on information comprising a value of the first syntax. The current block is encoded at the encoder side or decoded at the decoder side according to the target coding mode. The high level may correspond to a slice header or a picture header.

Abstract: An electronic device and a method for detecting abnormal device operation are provided. The method includes: obtaining multiple action events of a movable input device, and each action event including a relative coordinate and a time stamp of the movable input device; generating multiple absolute coordinates based on the relative coordinate of each action event; estimating multiple speed vectors based on the absolute coordinates and the time stamp of each action event; estimating multiple acceleration vectors based on the speed vectors and the time stamp of each action event; and estimating a probability of abnormal operation based on the speed vectors and the acceleration vectors.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.

Abstract: An image control device and an image control method are provided. The image control device includes a control command output port, an image input port, a processor and an image output unit. The control command output port transmits a scene switching command to an image source device; the image input port receives an image stream from the image source device; the processor is coupled to the image input port and the control command output port to retrieve a first image and a second image from the image stream, wherein the second image corresponds to the scene switching command; the image output unit is coupled to the processor and outputs the first image and the second image, wherein the first image is displayed in a first display area and the second image is displayed in a second display area.

Abstract: An image control device and an image control method are provided. The image control device includes a control command output port, an image input port, a processor and an image output unit. The control command output port transmits a scene switching command to an image source device; the image input port receives an image stream from the image source device; the processor is coupled to the image input port and the control command output port to retrieve a first image and a second image from the image stream, wherein the second image corresponds to the scene switching command; the image output unit is coupled to the processor and outputs the first image and the second image, wherein the first image is displayed in a first display area and the second image is displayed in a second display area.

Abstract: A method for planarizing a semiconductor device includes steps herein. A substrate is provided, on which a stop layer is formed. A trench is formed in the substrate. A first semiconductor film is deposited conformally on the stop layer and the trench. A second semiconductor film is deposited to fill the trench and cover the first semiconductor film. A chemical-mechanical polishing process is performed until the stop layer is exposed. A removal rate of the chemical-mechanical polishing process on the first semiconductor film is higher than that on the second semiconductor film. The first dielectric layer on the substrate selectively is removed.

Abstract: A method for planarizing a semiconductor device includes steps herein. A substrate is provided, on which a stop layer is formed. A trench is formed in the substrate. A first semiconductor film is deposited conformally on the stop layer and the trench. A second semiconductor film is deposited to fill the trench and cover the first semiconductor film. A chemical-mechanical polishing process is performed until the stop layer is exposed. A removal rate of the chemical-mechanical polishing process on the first semiconductor film is higher than that on the second semiconductor film. The first dielectric layer on the substrate selectively is removed.

Abstract: A method of forming an STI structure is described. A patterned mask layer is formed over a substrate of a wafer. A portion of the substrate exposed by the patterned mask layer is removed to form trenches. A dielectric layer is formed over the substrate filling the trenches. A first CMP process is performed to remove a portion of the dielectric layer. A second CMP process is performed to remove a further portion of the dielectric layer and a portion of the patterned mask layer, such that the surface of the dielectric layer is lower than that of the patterned mask layer. The polishing rate in the second CMP process is lower than that in the first one. The polishing selectivity of the dielectric layer to the mask layer in the second CMP process is higher than that in the first one. The patterned mask layer is then removed.

Abstract: A CMP process is provided. A first polishing process on a wafer is performed using a first hard polishing pad with a first slurry. Then, a buffering process on the wafer is performed using a soft polishing pad with a cleaning agent to buffer the pH value in the first polishing process and to remove at least portion of the first slurry and the cleaning agent by the contact with the first soft polishing pad simultaneously. Thereafter, a second polishing process on the wafer is performed using a second hard polishing pad with a second slurry such that the pH value after the buffering process is between the pH value in the first polishing process and the pH value in the second polishing process. The method can avoid the scratch issue of wafer surface by particles resulting from pH shock and cross contamination.

Abstract: A CMP process is provided. A first polishing process on a wafer is performed using a first hard polishing pad with a first slurry. Then, a buffering process on the wafer is performed using a soft polishing pad with a cleaning agent to buffer the pH value in the first polishing process and to remove at least portion of the first slurry and the cleaning agent by the contact with the first soft polishing pad simultaneously. Thereafter, a second polishing process on the wafer is performed using a second hard polishing pad with a second slurry such that the pH value after the buffering process is between the pH value in the first polishing process and the pH value in the second polishing process. The method can avoid the scratch issue of wafer surface by particles resulting from pH shock and cross contamination.