Patents by Inventor TZU-YI LIN

TZU-YI LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12002867
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: June 4, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hung Chu, Shuen-Shin Liang, Hsu-Kai Chang, Tzu Pei Chen, Kan-Ju Lin, Chien Chang, Hung-Yi Huang, Sung-Li Wang
  • Publication number: 20240178102
    Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: May 30, 2024
    Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
  • Publication number: 20240178090
    Abstract: A package structure including a semiconductor die, a redistribution layer structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution layer structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution layer structure includes a backside dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the backside dielectric layer and the inter-dielectric layers. The electronic device is disposed over the backside dielectric layer and electrically connected to an outermost redistribution conductive layer among the redistribution conductive layers, wherein the outermost redistribution conductive layer is embedded in the backside dielectric layer, and the backside dielectric layer comprises a ring-shaped recess covered by the outermost redistribution conductive layer.
    Type: Application
    Filed: February 7, 2023
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Tzu-Sung Huang, Hao-Yi Tsai, Ming-Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin
  • Publication number: 20240178091
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Publication number: 20240178120
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.
    Type: Application
    Filed: February 8, 2023
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Tzu-Sung Huang, Wei-Kang Hsieh, Hao-Yi Tsai, Ming-Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Chu-Chun Chueh
  • Publication number: 20240175900
    Abstract: A probe head includes a probe seat, and vertical probes each having a head portion including a head portion installation section with a first width, and a probe tip section including a probe tip contact part with a second width smaller than the first width and a probe tip gradually narrowing part which is located between the head portion installation section and the probe tip contact part, gradually narrows from the first width to the second width, and has a first length smaller than a second length of the probe tip contact part. The head portion installation section protrudes out of a lower surface of the probe seat for a length smaller than the sum of the first and second lengths. The vertical probe is great in current withstanding capability, structural strength and life time, and meets the requirement of probing tiny electrically conductive contacts.
    Type: Application
    Filed: November 24, 2023
    Publication date: May 30, 2024
    Applicant: MPI CORPORATION
    Inventors: CHIN-YI LIN, TZU-YANG CHEN, TZU-HAO CHIEN, CHAO-SHUN WANG, LI-MING FAN
  • Publication number: 20240179311
    Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Chia-Ming TSAI, Tzu-Der CHUANG, Chih-Wei HSU, Ching-Yeh CHEN, Zhi-Yi LIN
  • Patent number: 11996472
    Abstract: A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.
    Type: Grant
    Filed: February 9, 2023
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ya-Yi Tsai, Chi-Hsiang Chang, Shih-Yao Lin, Tzu-Chung Wang, Shu-Yuan Ku
  • Publication number: 20240145650
    Abstract: A package comprises a substrate including a first surface, and an upper conductive layer arranged on the first surface, a first light-emitting unit arranged on the upper conductive layer, and comprises a first semiconductor layer, a first substrate, a first light-emitting surface and a first side wall, a second light-emitting unit, which is arranged on the upper conductive layer, and comprises a second light-emitting surface and a second side wall, a light-transmitting layer arranged on the first surface and covers the upper conductive layer, the first light-emitting unit, and the second light-emitting unit, a light-absorbing layer, which is arranged between the substrate and the light-transmitting layer in a continuous configuration of separating the first light-emitting unit and the second light-emitting unit from each other, and a reflective wall arranged on the first side wall, wherein a height of the reflective wall is lower than that of the light-absorbing layer.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Inventors: Shau-Yi CHEN, Tzu-Yuan LIN, Wei-Chiang HU, Pei-Hsuan LAN, Min-Hsun HSIEH
  • Patent number: 11973958
    Abstract: Methods and apparatus of video coding using sub-block based affine mode are disclosed. According to this method, control-point motion vectors (MVs) associated with the affine mode are determined for a block. A sub-block MV is derived for a target sub-block of the block from the control-point MVs for the block. A prediction offset is determined for a target pixel of the target sub-block using information comprising a pixel MV offset from the sub-block MV for the target pixel according to Prediction Refinement with Optical Flow (PROF). The target pixel of the target sub-block is encoded or decoded using a modified predictor. The modified prediction is generated by clipping the prediction offset to a target range and combining the clipped prediction offset with an original predictor.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 30, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Tzu-Der Chuang, Ching-Yeh Chen, Zhi-Yi Lin
  • Publication number: 20240113166
    Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.
    Type: Application
    Filed: February 15, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ging Lin, Chun-Liang Lai, Yun-Chen Wu, Ya-Yi Tsai, Shu-Yuan Ku, Shun-Hui Yang
  • Patent number: 11949852
    Abstract: A method and apparatus of video coding, where according to one method, input data related to a current block in a current picture are received at a video encoder side or compressed data comprising the current block are received at a video decoder side. A first syntax at a high level in a video bitstream regarding residual coding type is signaled at the encoder side or parsed at the decoder side. A target coding mode is determined for the current block based on information comprising a value of the first syntax. The current block is encoded at the encoder side or decoded at the decoder side according to the target coding mode. The high level may correspond to a slice header or a picture header.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: April 2, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Zhi-Yi Lin, Tzu-Der Chuang, Ching-Yeh Chen
  • Patent number: 11935804
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Patent number: 11930174
    Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 12, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Tzu-Der Chuang, Chih-Wei Hsu, Ching-Yeh Chen, Zhi-Yi Lin
  • Patent number: 11794360
    Abstract: An electric knife includes a cutter blade, a handle, and a drive unit and a driven unit mounted inside the handle. The drive unit includes a first movable sleeve. The driven unit includes a second movable sleeve. The cutter blade is set on the second movable sleeve. The drive unit and the driven unit are connected through a link, so that the drive unit can drive the second movable sleeve of the driven unit and the cutter blade to reciprocate along an axis.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: October 24, 2023
    Assignee: CUTTWAY PRODUCTS CO.,LTD.
    Inventors: Yi-Yang Chang, Tzu-Yi Lin
  • Publication number: 20230158626
    Abstract: An electric knife sharpener includes an accommodating unit including a base and an upper cover with a V-shaped opening slot, a driving unit fixed on the base and including a motor and an eccentric wheel, a linkage unit including a linkage mechanism and an upper fixing seat with two limiting rods thereof pivotally connected to an upper part of the upper fixing seat, and a grinding unit. The linkage unit has a guide groove located in a pivot end thereof and coupled to two guiding blocks in a through hole of the upper fixing seat. The grinding unit includes two sharpening components. One end of each sharpening component is pivotally connected in a groove of the linkage mechanism, so that the two sharpening components form a cross arrangement and opposite openings are formed between the two sharpening components to cross a sharpening accommodating space.
    Type: Application
    Filed: December 8, 2021
    Publication date: May 25, 2023
    Applicant: CUTTWAY PRODUCTS CO.,LTD.
    Inventors: Tzu-Yi LIN, Po-Chun CHUANG
  • Publication number: 20230158627
    Abstract: An electric knife sharpener includes an accommodating unit including a base and an upper cover with an opening slot, a driving unit fixed on the base and including a motor and an eccentric wheel, a linkage unit including a linkage mechanism and an upper fixing seat with two limiting rods thereof pivotally connected to an upper part of the upper fixing seat in a parallel manner, and a grinding unit. The linkage unit has a guide groove located in a pivot end thereof and coupled to two guiding blocks in a through hole of the upper fixing seat. When the linkage mechanism is drivable by the eccentric wheel to move up and down alternatively. The grinding unit includes two sharpening components. One end of each sharpening component is pivotally connected in a groove of the linkage mechanism, so that the two sharpening components form a cross arrangement and opposite openings are formed between the two sharpening components to cross a sharpening accommodating space.
    Type: Application
    Filed: September 2, 2022
    Publication date: May 25, 2023
    Applicant: CUTTWAY PRODUCTS CO.,LTD.
    Inventors: Tzu-Yi LIN, Po-Chun CHUANG
  • Publication number: 20230145219
    Abstract: An electric knife includes a cutter blade, a handle, and a drive unit and a driven unit mounted inside the handle. The drive unit includes a first movable sleeve. The driven unit includes a second movable sleeve. The cutter blade is set on the second movable sleeve. The drive unit and the driven unit are connected through a link, so that the drive unit can drive the second movable sleeve of the driven unit and the cutter blade to reciprocate along an axis.
    Type: Application
    Filed: December 3, 2021
    Publication date: May 11, 2023
    Applicant: CUTTWAY PRODUCTS CO.,LTD.
    Inventors: Yi-Yang Chang, Tzu-Yi Lin
  • Publication number: 20220036490
    Abstract: A method of validating learning outcomes of a student is disclosed. In the method, a teaching application includes a validation program to determine an execution score and a completion rate for the student's execution result, the teaching application includes a task database storing task packages which are teaching contents previously taught to the student, and the task package include a sub-task package for the student to execute tasks, the sub-task package includes a validation program for acceptance of the execution result and statistics of an execution score and a completion rate. According to the insufficiency of the student in response to the student's execution score and the completion rate displayed on the teaching application, the teaching application automatically assigns the student to challenge the failed task again or assigns a remedial task to the student, so as to improve the student in knowledge or skills learned in course.
    Type: Application
    Filed: May 5, 2021
    Publication date: February 3, 2022
    Inventors: Chih-Wei CHAN, Tzu-Yi LIN
  • Publication number: 20210263376
    Abstract: A flexible display device having a bending region is provided by the present disclosure. The flexible display device includes a display panel, a first polarizer and a second polarizer disposed under the display panel. The first polarizer is disposed on the display panel and includes a first conductive layer and a first optical layer, wherein the first conductive layer is disposed between the first optical layer and the display panel.
    Type: Application
    Filed: January 18, 2021
    Publication date: August 26, 2021
    Inventors: Hsin-Hao Huang, Tzu-Yi Lin, Chu-Hong Lai