Patents by Inventor Tzu Yin Wei

Tzu Yin Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11749374
    Abstract: A memory device includes a memory cell array, a data accessing circuit, a data bus inversion calculator, a multiplexer, and an output result judging circuit. The data accessing circuit performs a data write-in operation or a data read-out operation on the memory cell array. The data accessing circuit reads read-out data from the memory cell array. The data bus inversion calculator generates inversion indication data according to the read-out data. The multiplexer outputs the inversion indication data or test data according to a mode signal. The output result judging circuit compares the read-out data with the inversion indication data or the test data to generate output information.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: September 5, 2023
    Assignee: Winbond Electronics Corp.
    Inventor: Tzu-Yin Wei
  • Publication number: 20230268021
    Abstract: A memory device includes a memory cell array, a data accessing circuit, a data bus inversion calculator, a multiplexer, and an output result judging circuit. The data accessing circuit performs a data write-in operation or a data read-out operation on the memory cell array. The data accessing circuit reads read-out data from the memory cell array. The data bus inversion calculator generates inversion indication data according to the read-out data. The multiplexer outputs the inversion indication data or test data according to a mode signal. The output result judging circuit compares the read-out data with the inversion indication data or the test data to generate output information.
    Type: Application
    Filed: February 22, 2022
    Publication date: August 24, 2023
    Applicant: Winbond Electronics Corp.
    Inventor: Tzu-Yin Wei
  • Patent number: 9799391
    Abstract: A DRAM circuit includes an array having a normal word line, a first redundant word line and a second redundant word line immediately adjacent to the first redundant word line. The second redundant word line is activated if the normal word line is assigned, by a memory controller external to the DRAM circuit, to be activated. A redundant refresh circuit is configured to determine that the first redundant word line is required to be refreshed in response to the second redundant word line being activated; and a row decoder is configured to, according to the determination of the redundant refresh circuit, refresh the first redundant word line.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: October 24, 2017
    Assignee: Nanya Technology Corporation
    Inventor: Tzu Yin Wei