Abstract: A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The first active region forms, together with the initial cell, a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. The positioning the first active region is executed by a processor.

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

Abstract: A method includes disposing a first power rail, a second power rail and a third power rail arranged in order; disposing a first cell row having a first row height between the first power rail and the second power rail; and disposing a second cell row having the first row height between the third power rail and the second power rail. Each of the first power rail and the third power rail has a first width, and the second power rail has a second width larger than the first width.

Abstract: An integrated circuit disclosed here includes a first plurality of cell rows, a second plurality of cell rows, first and second clock inverters, and a plurality of flip-flops. The second plurality of cell rows are arranged abutting the first plurality of cell rows. A first number of fins in the first plurality of cell rows is different from a second number of fins in the second plurality of cell rows. The first and second clock inverters are arranged in the second plurality of cell rows. The plurality of flip-flops are arranged in the first plurality of cell rows and the second plurality of cell rows. The plurality of flip-flops include a first plurality of flip-flops configured to operate in response to the first clock and second clock signals.

Abstract: An integrated circuit provided here includes a N-bit flip-flop and a first clock cell. The N-bit flip-flop includes first cell of a first bit and a second cell of a second bit. An output signal from the first cell is inputted into the second cell in response to a first clock signal. The first and second cells have different widths and are arranged in a first row of multiple first cell rows and a first row of multiple second cell rows respectively. The first cell rows and the second cell rows have different row heights. The first clock cell outputs the first clock signal and is arranged in the first row of the second cell rows to abut the first cell.

Abstract: A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.

Abstract: A system includes a non-transitory storage medium encoded with a set of instructions and a processor. The processor is configured to execute the set of instructions. The set of instructions is configured to cause the processor to: obtain, based on a netlist of a circuit, values each corresponding to one of transistors included in the circuit; compare the values with a threshold value; in response to a comparison, generate an adjusted netlist of the circuit by adding redundant transistors; and determine, based on the adjusted netlist, one of layout configurations for the circuit. The layout configurations include first cell rows each having a first row height and second cell rows each having a second row height different from the first row height.

Abstract: A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a first latching circuit and a second latching circuit coupled to the first latching circuit. The second latching circuit includes a first feedback circuit and a first transmission circuit, the first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and the first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.

Abstract: A semiconductor device includes several first cell rows extending in a first direction, each of the first cell rows having a first row height; several second cell rows extending in the first direction, each of the second cell rows having a second row height smaller than the first row height, wherein the first cell rows and the second cell rows are interlaced; a first cell arranged in a first row of the first cell rows; and at least one second cell arranged in at least one row of the second cell rows, wherein the at least one second cell abuts the first cell in a second direction different from the first direction, wherein the at least one second cell and at least one circuit component included in the first cell have the same operation configuration.

Abstract: A UV LED package includes a substrate having a dam, a LED die on the substrate, a lens bonded to the substrate, an extraction layer covering a light emitting surface of the LED die, and a lens sealing layer between the lens and the dam. The extraction layer can be formed to provide a precise gap G between the lens and the light emitting diode (LED). In addition, the materials for the lens and the extraction layer can be selected, and the gap G can be precisely dimensioned, to reduce refraction and reflection, to improve radiation extraction, to reduce power radiance, and to improve the efficiency of the UV LED package.

Abstract: A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.

Abstract: A positive-pressure protective wear has a protective body and an air supply. The protective body has a clothing and a headgear connected with the clothing. The air supply is connected with the protective body and inputs gas into the protective body to keep the protective body under positive pressure, and this can provide an effect of ventilation.

Abstract: An integrated circuit disclosed here includes a first plurality of cell rows, a second plurality of cell rows, first and second clock inverters, and a plurality of flip-flops. The second plurality of cell rows are arranged abutting the first plurality of cell rows. A first number of fins in the first plurality of cell rows is different from a second number of fins in the second plurality of cell rows. The first and second clock inverters are arranged in the second plurality of cell rows. The plurality of flip-flops are arranged in the first plurality of cell rows and the second plurality of cell rows. The plurality of flip-flops include a first plurality of flip-flops configured to operate in response to the first clock and second clock signals.

Abstract: A semiconductor device includes several first cell rows extending in a first direction, each of the first cell rows having a first row height; several second cell rows extending in the first direction, each of the second cell rows having a second row height smaller than the first row height, wherein the first cell rows and the second cell rows are interlaced; a first cell arranged in a first row of the first cell rows; and at least one second cell arranged in at least one row of the second cell rows, wherein the at least one second cell abuts the first cell in a second direction different from the first direction, wherein the at least one second cell and at least one circuit component included in the first cell have the same operation configuration.

Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

Abstract: A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The first active region forms, together with the initial cell, a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. The positioning the first active region is executed by a processor.

Abstract: A UV LED package includes a substrate having a dam, a LED die on the substrate, a lens bonded to the substrate, an extraction layer covering a light emitting surface of the LED die, and a lens sealing layer between the lens and the dam. The extraction layer can be formed to provide a precise gap G between the lens and the light emitting diode (LED). In addition, the materials for the lens and the extraction layer can be selected, and the gap G can be precisely dimensioned, to reduce refraction and reflection, to improve radiation extraction, to reduce power radiance, and to improve the efficiency of the UV LED package.

Abstract: A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The method further includes arranging at least one first fin feature in the first active region, to obtain a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. At least one of the positioning the first active region or the arranging the at least one first fin feature is executed by a processor.