Patents by Inventor Tzu-Yu Cheng

Tzu-Yu Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210028108
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Application
    Filed: October 8, 2020
    Publication date: January 28, 2021
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 10872873
    Abstract: A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Chih Chen, Tsung-Yi Yang, Chung-I Hung, Mu-Han Cheng, Tzu-Shin Chen, Su-Yu Yeh
  • Patent number: 10868353
    Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Hsiu-Jen Lin, Hsuan-Ting Kuo, Kai-Chiang Wu, Ming-Che Ho, Wei-Yu Chen, Yu-Peng Tsai, Chia-Lun Chang, Chia-Shen Cheng, Chih-Chiang Tsao, Tzu-Chun Tang, Ching-Hua Hsieh, Tuan-Yu Hung, Cheng-Shiuan Wong
  • Patent number: 10804200
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Publication number: 20200292157
    Abstract: A light-emitting device including a substrate with a top surface and a bottom surface opposite to the top surface and a plurality of LED chips disposed on the top surface and configured to generate a top light visible above the top surface and a bottom light visible beneath the bottom surface, each LED chip comprising a plurality of light-emitting surfaces. The substrate has a thickness greater than 200 ?m and comprises aluminum oxide, sapphire, glass, plastic, or rubber. The plurality of LED chips has an incident light with a wavelength of 420-470 nm. The top light and the bottom light have a color temperature difference of not greater than 1500K.
    Type: Application
    Filed: May 29, 2020
    Publication date: September 17, 2020
    Inventors: CHI-CHIH PU, CHEN-HONG LEE, SHIH-YU YEH, WEI-KANG CHENG, SHYI-MING PAN, SIANG-FU HONG, CHIH-SHU HUANG, TZU-HSIANG WANG, SHIH-CHIEH TANG, CHENG-KUANG YANG
  • Publication number: 20200279068
    Abstract: A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, the information including a mean of slacks and a sigma of slacks of each of the paths; determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma; dividing the paths into groups based on SM values, an SM value of a path in one of the groups being different from that of a path in another one of the groups; and determining a yield requirement that indicates the maximum number of paths allowable in each group in order to achieve a predetermined yield.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: YEN-PIN CHEN, TZU-HEN LIN, TAI-YU CHENG, FLORENTIN DARTU, CHUNG-HSING WANG
  • Publication number: 20200227570
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation layer formed over a substrate, and a plurality of nanostructures formed over the isolation layer. The semiconductor device structure includes a gate structure wrapped around the nanostructures, and an S/D structure wrapped around the nanostructures. The semiconductor device structure includes a first oxide layer between the substrate and the S/D structure. The first oxide layer and the isolation layer are made of different materials. The first oxide layer is in direct contact with the isolation layer.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hou-Yu CHEN, Chao-Ching CHENG, Tzu-Chiang CHEN, Yu-Lin YANG, I-Sheng CHEN
  • Patent number: 10678989
    Abstract: A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, wherein the information includes a mean of slacks and a sigma of slacks of each of the paths, determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma, and determining that a first path of the paths is more critical than a second path of the paths, an SM value of the first path being smaller than that of the second path.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Pin Chen, Tzu-Hen Lin, Tai-Yu Cheng, Florentin Dartu, Chung-Hsing Wang
  • Patent number: 10670244
    Abstract: The present invention relates to a light emitting device comprising a transparent substrate which light can pass through and at least one LED chip emitting light omni-directionally. Wherein the LED chip is disposed on one surface of the substrate and the light emitting angle of the LED chip is wider than 180°, and the light emitted by the LED chip will penetrate into the substrate and at least partially emerge from another surface of the substrate. According to the present invention, the light emitting device using LED chips can provide sufficient lighting intensity and uniform lighting performance.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: June 2, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chi-Chih Pu, Chen-Hong Lee, Shih-Yu Yeh, Wei-Kang Cheng, Shyi-Ming Pan, Siang-Fu Hong, Chih-Shu Huang, Tzu-Hsiang Wang, Shih-Chieh Tang, Cheng-Kuang Yang
  • Publication number: 20200106156
    Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.
    Type: Application
    Filed: April 18, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Hsiu-Jen Lin, Hsuan-Ting Kuo, Kai-Chiang Wu, Ming-Che Ho, Wei-Yu Chen, Yu-Peng Tsai, Chia-Lun Chang, Chia-Shen Cheng, Chih-Chiang Tsao, Tzu-Chun Tang, Ching-Hua Hsieh, Tuan-Yu Hung, Cheng-Shiuan Wong
  • Patent number: 10515166
    Abstract: A method includes identifying the first path as a target path, wherein an operation speed of the target path is adjusted from the corner case; deriving and outputting first values from the lookup table by indexing the lookup table with a threshold voltage associated with the first path identified as the target path as the main threshold voltage and a threshold voltage associated with the second path as the slave threshold voltage; calculating a first extra time based on the first values and first cell delays associated with the first path.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Pin Chen, Tai-Yu Cheng, Tzu-Hen Lin, Chung-Hsing Wang
  • Publication number: 20190219252
    Abstract: The present invention relates to a light emitting device comprising a transparent substrate which light can pass through and at least one LED chip emitting light omni-directionally. Wherein the LED chip is disposed on one surface of the substrate and the light emitting angle of the LED chip is wider than 180°, and the light emitted by the LED chip will penetrate into the substrate and at least partially emerge from another surface of the substrate. According to the present invention, the light emitting device using LED chips can provide sufficient lighting intensity and uniform lighting performance.
    Type: Application
    Filed: March 26, 2019
    Publication date: July 18, 2019
    Inventors: CHI-CHIH PU, CHEN-HONG LEE, SHIH-YU YEH, WEI-KANG CHENG, SHYI-MING PAN, SIANG-FU HONG, CHIH-SHU HUANG, TZU-HSIANG WANG, SHIH-CHIEH TANG, CHENG-KUANG YANG
  • Publication number: 20190180704
    Abstract: A display apparatus and a driving method of a display panel are provided. A display driver drives the display panel so that the adjacent pixels in each of first display segments and each of the second display segments on a scan line have opposite polarities, and two pixels located on junction section of adjacent first display segment and second display segment have the same polarity.
    Type: Application
    Filed: May 4, 2018
    Publication date: June 13, 2019
    Applicant: Au Optronics Corporation
    Inventors: Mei-Chun Cheng, Zun-Yu Wang, Chia-Chu Wang, Yi-Ping Huang, Hao-Ren Gu, Tzu-Han Fang
  • Patent number: 10317462
    Abstract: An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. The wide-range test clock signal is generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: June 11, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Tzu-Heng Huang
  • Patent number: 10296115
    Abstract: A touch display apparatus having a fan-out side is provided. The touch display apparatus includes a first substrate, a second substrate, a touch sensing element and a display element. The first and the second substrate have a first surface and a second inner surface, respectively. The second substrate is disposed opposite to the first substrate. The second inner surface faces the first inner surface. The second substrate has a convex part and a concave part on the fan-out side. The second inner surface has a second outer lead bonding region in the convex part. The first outer lead bonding region of the first substrate is unshielded by the second substrate through the concave part. The second outer lead bonding region of the second substrate is unshielded by the first substrate. The touch sensing element and the display element are packaged in between the first and the second substrates.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: May 21, 2019
    Assignee: AU OPTRONICS CORP.
    Inventors: Chun-Chi Lai, Chee-Wai Lau, Feng-Sheng Lin, Yi-Ru Su, Chi-Chun Liao, Rong-Ann Lin, Chia-Ping Lu, An-Hsiung Hsieh, Pei-Yu Chen, Tsang Hong Wang, Tzu-Chi Tseng, Chung-Hao Cheng, Hsu Sheng Hsu
  • Publication number: 20190148333
    Abstract: A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 16, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Chih CHEN, Tsung-Yi YANG, Chung-I HUNG, Mu-Han CHENG, Tzu-Shin CHEN, Su-Yu YEH
  • Patent number: 10290514
    Abstract: An electronic product including a supporting structure, a first thermo-formable film, a conductive circuit and a protection layer is provided. The conductive circuit is formed on the first thermo-formable film, and an electronic component is mounted on the conductive circuit. The protection layer covers the electronic component, and includes a second thermo-formable film. The conductive circuit and the electronic component are enclosed between the first thermo-formable film and the second thermo-formable film, and the supporting structure, the first thermo-formable film and the protection layer are bonded and stacked to each other.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: May 14, 2019
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Yi-Feng Pu, Po-Yu Cheng, Tzu-Shu Lin
  • Publication number: 20190096592
    Abstract: A method of manufacturing a composite material is provided. First, graphene oxide and activated carbon are provided individually. Graphene oxide and activated carbon are added into an alcohol to form a mixture. Then, the mixture is heated by microwave in a single step, so that graphene oxide is chemically reduced to form graphene at the active sites of the surface of the activated carbon uniformly, thereby forming a composite material. The embodied composite material is suitable for being the electrodes of the capacitive deionization (CDI) and supercapacitor application.
    Type: Application
    Filed: December 22, 2017
    Publication date: March 28, 2019
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Li-Ching CHUNG, Po-I LIU, Chih-Hsiang FANG, Tzu-Yu CHENG, Hsin SHAO, Min-Chao CHANG, Ren-Yang HORNG, Teh-Ming LIANG, Nyan-Hwa TAI, Yi-Ting LAI
  • Publication number: 20190042037
    Abstract: A touch display panel operating in alternating touch-sensing modes includes a first substrate and a second substrate facing the first substrate, and with first electrodes on the first substrate and second electrodes on the second substrate. The touch display panel can work in a self-capacitance mode and a mutual-capacitance mode in sensing touch operations. The mutual-capacitance mode is implemented by the first electrodes and the second electrodes working together and the self-capacitance mode is implemented by the first electrodes alone.
    Type: Application
    Filed: May 24, 2018
    Publication date: February 7, 2019
    Inventors: CHIA-LIN LIU, YU-FU WENG, CHIEN-WEN LIN, TZU-YU CHENG
  • Patent number: D873834
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 28, 2020
    Assignee: ACER INCORPORATED
    Inventors: Ju-Hsien Weng, Tzu-Hsiang Chang, Te-Ho Chen, Hsing-Yi Kao, Chien-Yu Hsieh, Wei-Yi Li, Yi-Ming Chang, Lun-Yu Hung, Cheng-Yu Cheng