Patents by Inventor Tzu-Yu Lin

Tzu-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220379265
    Abstract: A filter device includes one or more filter membranes, and a filter housing enclosing the one or more filter membranes. Each of the filter membranes includes a base membrane and a plurality of through holes.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Inventors: Chwen YU, En Tian LIN, Chih-Chiang TSENG, Tzu-Sou CHUANG
  • Patent number: 11507240
    Abstract: A touch sensor comprises a first electrode, a second electrode arranged spaced apart from the first electrode, and an insulator arranged between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode is energized, and an energy difference exists between the first electrode and the second electrode. At least one of the first electrode and the second electrode is a stressed electrode. When the stressed electrode is not stressed, no electrical signal is generated, and when the stressed electrode is stressed, the stressed electrode deforms at a stressed point and changes the distance between the stressed point and the other electrode to generate a tunneling current, and the touch sensor generates the electrical signal according to whether the tunneling current is generated. Therefore, the invention solves a limitation of the conventional touch sensor in touching and provides good touching sensitivity.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: November 22, 2022
    Assignee: HIGGSTEC INC.
    Inventors: Yi-Han Wang, Tzu-Chien Lin, Chui-Xiang Chiou, Hung-Yu Tsai
  • Publication number: 20220367405
    Abstract: Methods and systems for improving fusion bonding are disclosed. Plasma treatment is performed on a substrate prior to the fusion bonding, which leaves residual charge on the substrate to be fusion bonded. The residual charge is usually dissipated through an electrically conductive silicone cushion on a loading pin. In the methods, the amount of residual voltage on a test silicon wafer is measured. If the residual voltage is too high, this indicates the usable lifetime of the silicone cushion has passed, and the electrically conductive silicone cushion is replaced. This ensures the continued dissipation of residual charge during use in production, improving the quality of fusion bonds between substrates.
    Type: Application
    Filed: February 8, 2022
    Publication date: November 17, 2022
    Inventors: Hong-Ta Kuo, Yen Hao Huang, I-Shi Wang, Ming-Yi Shen, Tzu-Ping Yang, Hsing-Yu Wang, Huang-Liang Lin, Yin-Tun Chou, Yuan-Hsin Chi, Sheng-Yuan Lin
  • Publication number: 20220367358
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 11493536
    Abstract: A probe head includes upper and lower die units, and a linear probe inserted therethrough and thereby defined with tail, body and head portions. A first bottom surface of the upper die unit and a second top surface of the lower die unit face each other, thereby defining an inner space wherein the body portion is located and includes a plurality of sections each having front width larger than or equal to back width, including a narrowest section whose upper and lower ends have a distance from the first bottom surface and the second top surface respectively. The head and tail portions are offset from each other along two horizontal axes and the body portion is thereby curved. The present invention is favorable in dynamic behavior control of the linear probe which is easy in manufacturing, lower in cost and has more variety in material.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: November 8, 2022
    Assignee: MPI CORPORATION
    Inventors: Tzu-Yang Chen, Chin-Yi Lin, Chen-Rui Wu, Sheng-Yu Lin, Ming-Ta Hsu, Chia-Ju Wei
  • Patent number: 11482012
    Abstract: A method for assisting a driver to drive a vehicle in a safer manner includes capturing images of road in front of the vehicle, and identifying a traffic sign in the images. A first image frame is captured at a first time and a second image frame is captured at a later second time when the images do comprise the traffic sign. A change in size or other apparent change of the traffic sign from the first image frame to the second image frame is determined, and conformity or non-conformity with a predetermined rule is then determined. The traffic sign can be analyzed and recognized to trigger the vehicle to perform an action accordingly when conformity is found. A device providing assistance with driving is also provided.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: October 25, 2022
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jung-Yi Lin, Chung-Yu Wu, Tzu-Chen Lin
  • Publication number: 20220334482
    Abstract: A patterning stack is provided. The patterning stack includes a bottom anti-reflective coating (BARC) layer over a substrate, a photoresist layer having a first etching resistance over the BARC layer, and a top coating layer having a second etching resistance greater than the first etching resistance over the photoresist layer. The top coating layer includes a polymer having a polymer backbone including at least one functional unit of high etching resistance and one or more acid labile groups attached to the polymer backbone or a silicon cage compound.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Inventors: Tzu-Yang LIN, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20220328508
    Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric random-access memory (FeRAM) cell or some other suitable type of memory cell comprising a bottom-electrode interface structure. The memory cell further comprises a bottom electrode, a switching layer over the bottom electrode, and a top electrode over the switching layer. The bottom-electrode interface structure separates the bottom electrode and the switching layer from each other. Further, the interface structure is dielectric and is configured to block or otherwise resist metal atoms and/or impurities in the bottom electrode from diffusing to the switching layer. By blocking or otherwise resisting such diffusion, leakage current may be decreased. Further, endurance of the memory cell may be increased.
    Type: Application
    Filed: June 14, 2021
    Publication date: October 13, 2022
    Inventors: Tzu-Yu Lin, Chia-Wen Zhong, Yao-Wen Chang
  • Publication number: 20220317408
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Publication number: 20220320307
    Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.
    Type: Application
    Filed: September 1, 2021
    Publication date: October 6, 2022
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Yee-Chia Yeo, Wei Hao Lu
  • Publication number: 20220320276
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Application
    Filed: August 5, 2021
    Publication date: October 6, 2022
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Publication number: 20220302201
    Abstract: Provided is a stacked luminescent device including a plurality of electroluminescent devices and a plurality of conductive lines. The electroluminescent devices are vertically stacked with each other to form a staircase structure on a staircase region. Each electroluminescent device includes a substrate, an encapsulation layer, and a quantum dot light-emitting diode (QLED) device sandwiched between the substrate and the encapsulation layer. The conductive lines are respectively connected to the QLED devices in the electroluminescence devices along the staircase structure. A method of manufacturing the stacked luminescent device is also provided.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 22, 2022
    Applicant: Hongyi Optical Co., Ltd.
    Inventors: Yao-Tang Chang, Tzu Yu Lin
  • Patent number: 11451154
    Abstract: A flyback power converter circuit includes: a power transformer, a primary side switch and a conversion control circuit. In a DCM, during a dead time, the conversion control circuit calculates an upper limit frequency corresponding to output current according to a frequency upper limit function, and obtains a frequency upper limit masking period according to a reciprocal of the upper limit frequency, wherein the frequency upper limit masking period is a period starting from when the primary side switch is turned ON. During an upper limit selection period, the conversion control circuit selects a valley among one or more valleys in a ringing signal related to a voltage across the primary side switch as an upper limit locked valley, so that the conversion control circuit once again turns ON the primary side switch at a beginning time point of the upper limit locked valley.
    Type: Grant
    Filed: May 30, 2021
    Date of Patent: September 20, 2022
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Kun-Yu Lin, Tzu-Chen Lin, Wei-Hsu Chang, Ta-Yung Yang
  • Publication number: 20220285374
    Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.
    Type: Application
    Filed: May 3, 2021
    Publication date: September 8, 2022
    Inventors: Bi-Shen Lee, Tzu-Yu Lin, Yi Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Patent number: 11435024
    Abstract: A rebounding pivot module includes a mounting shaft, and a bouncing device set including a barrel having one end tooth shaped, a connecting tube mounted in the other end of the barrel, a connection rod connected to the connecting tube, a socket and a first guide block mounted onto the connection rod, the first guide block having one end beveled, a bouncing barrel mounted around the connecting rod, a second guide block supported on an elastic member in the bouncing barrel and defining therein a guide hole and having one end tooth shaped and abutted at the beveled edge of the first guide block, and a lock device fastened to connection rod that is inserted through the second guide block, the elastic member and the through hole of the bouncing barrel to lock the bouncing barrel to the connection rod.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 6, 2022
    Assignee: LIANHONG ART CO., LTD.
    Inventors: Chia-Hui Chen, Tzu-Yu Lin, Yen-Ting Chen
  • Patent number: 11437319
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Publication number: 20220277933
    Abstract: A wafer treatment system is provided. The wafer treatment system includes a wafer treatment chamber defining a treatment area within which a wafer is treated. The wafer treatment system includes a gas injection system. The gas injection system includes a gas injector configured to inject a first gas, used for treatment of the wafer, into the treatment area. A first gas tube is configured to conduct the first gas at a first temperature to the gas injector. The gas injection system includes a heating enclosure enclosing the gas injector. A second gas tube is configured to conduct a heated gas to the heating enclosure to increase an enclosure temperature at the heating enclosure to a second enclosure temperature. A temperature of the first gas is increased in the gas injector from the first temperature to a second temperature due to the second enclosure temperature at the heating enclosure.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Po Hsun CHEN, Chun Wei CHOU, Keng-Ying LIAO, Tzu-Pin LIN, Tai Chin WU, Su-Yu YEH, Po-Zen CHEN
  • Publication number: 20220278115
    Abstract: Ferroelectric stacks are disclosed herein that can improve retention performance of ferroelectric memory devices. An exemplary ferroelectric stack has a ferroelectric switching layer (FSL) stack disposed between a first electrode and a second electrode. The ferroelectric stack includes a barrier layer disposed between a first FSL and a second FSL, where a first crystalline condition of the barrier layer is different than a second crystalline condition of the first FSL and/or the second FSL. In some embodiments, the first crystalline condition is an amorphous phase, and the second crystalline condition is an orthorhombic phase. In some embodiments, the first FSL and/or the second FSL include a first metal oxide, and the barrier layer includes a second metal oxide. The ferroelectric stack can be a ferroelectric capacitor, a portion of a transistor, and/or connected to a transistor in a ferroelectric memory device to provide data storage in a non-volatile manner.
    Type: Application
    Filed: July 26, 2021
    Publication date: September 1, 2022
    Inventors: Yi Yang Wei, Tzu-Yu Lin, Bi-Shen Lee, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
  • Publication number: 20220246567
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.
    Type: Application
    Filed: June 2, 2021
    Publication date: August 4, 2022
    Inventors: Tzu-Yu Lin, Yao-Wen Chang, Chia-Wen Zhong, Yen-Liang Lin
  • Publication number: 20220246852
    Abstract: Provided is a method of manufacturing an electroluminescent device including: forming a first electrode layer on a substrate; forming a hole transport layer on the first electrode layer; forming a light emitting layer on the hole transport layer by using a transfer printing process; forming an electron transport layer on the light emitting layer; and forming a second electrode layer on the electron transport layer. Therefore, in the present disclosure, the manufacturing method of forming the light-emitting layer through the transfer printing process has the advantage of rapid manufacturing, and is suitable for manufacturing light emitting devices with a large area and any shape.
    Type: Application
    Filed: July 27, 2021
    Publication date: August 4, 2022
    Applicant: Hongyi Optical Co., Ltd.
    Inventors: Yao-Tang Chang, Tzu Yu Lin