Patents by Inventor Tzu-Yu Liu

Tzu-Yu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200124971
    Abstract: The present disclosure provides NTD developers and corresponding lithography techniques that can overcome resolution, line edge roughness (LER), and sensitivity (RLS) tradeoff barriers particular to extreme ultraviolet (EUV) technologies, thereby achieving high patterning fidelity for advanced technology nodes. An exemplary lithography method includes forming a negative tone resist layer over a workpiece; exposing the negative tone resist layer to EUV radiation; and removing an unexposed portion of the negative tone resist layer in a negative tone developer, thereby forming a patterned negative tone resist layer. The negative tone developer includes an organic solvent having a log P value greater than 1.82. The organic solvent is an ester acetate derivative represented by R1COOR2. R1 and R2 are hydrocarbon chains having four or less carbon atoms. In some implementations, R1, R2, or both R1 and R2 are propyl functional groups, such as n-propyl, isopropyl, or 2-methylpropyl.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Chen-Yu Liu, Wei-Han Lai, Tzu-Yang Lin, Ming-Hui Weng, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20200098558
    Abstract: A method is provided including forming a first layer over a substrate and forming an adhesion layer over the first layer. The adhesion layer has a composition including an epoxy group. A photoresist layer is formed directly on the adhesion layer. A portion of the photoresist layer is exposed to a radiation source. The composition of the adhesion layer and the exposed portion of the photoresist layer cross-link using the epoxy group. Thee photoresist layer is then developed (e.g., by a negative tone developer) to form a photoresist pattern feature, which may overlie the formed cross-linked region.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Inventors: Chen-Yu LIU, Tzu-Yang LIN, Ya-Ching CHANG, Ching-Yu CHANG, Chin-Hsiang LIN
  • Patent number: 10562148
    Abstract: A method of controlling processing of a substrate includes generating, based on a signal from an in-situ monitoring system, first and second sequences of characterizing values indicative of a physical property of a reference zone and a control zone, respectively, on a substrate. A reference zone rate and a control zone rate are determined from the first and sequence of characterizing values, respectively. An error value is determined by comparing characterizing values for the reference zone and control zone. An output parameter value for the control zone is generated based on at least the error value and a dynamic nominal control zone value using a proportional-integral-derivative control algorithm, and the dynamic nominal control zone value is generated in a second control loop based on at least the reference zone rate and the control zone rate. The control zone of the substrate is processed according to the output parameter value.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: February 18, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Shih-Haur Shen, Kun Xu, Tzu-Yu Liu
  • Patent number: 10556315
    Abstract: A method of controlling polishing includes polishing a substrate at a first polishing station, monitoring the substrate with a first eddy current monitoring system to generate a first signal, determining an ending value of the first signal for an end of polishing of the substrate at the first polishing station, determining a first temperature at the first polishing station, polishing the substrate at a second polishing station, monitoring the substrate with a second eddy current monitoring system to generate a second signal, determining a starting value of the second signal for a start of polishing of the substrate at the second polishing station, determining a gain for the second polishing station based on the ending value, the starting value and the first temperature, and calculating a third signal based on the second signal and the gain.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: February 11, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Kun Xu, Shih-Haur Shen, Boguslaw A. Swedek, Ingemar Carlsson, Doyle E. Bennett, Wen-Chiang Tu, Hassan G. Iravani, Tzu-Yu Liu
  • Publication number: 20200020729
    Abstract: A photo diode includes a pixel unit, a photo conversion layer, and a dielectric layer. The pixel unit includes a pair of pixels. The photo conversion layer is above the pixel unit and has a pair of portions, each of which corresponds to a respective one of the pixels. The dielectric layer is between the portions of the photo conversion layer. A method of manufacturing the photo diode is also disclosed.
    Type: Application
    Filed: September 23, 2019
    Publication date: January 16, 2020
    Inventors: Tzu-Jui Wang, Keng-Yu Chou, Chun-Hao Chuang, Ming-Chieh Hsu, Ren-Jie Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20200006105
    Abstract: An apparatus having a first portion including first front wall, first rear wall, and bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having second front wall, second rear wall, and top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between an open and closed configurations.
    Type: Application
    Filed: June 21, 2019
    Publication date: January 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Cheng KO, Tzu-Chong TSAI, Jhih-Yuan YANG, Fang-yu LIU
  • Patent number: 10520820
    Abstract: The present disclosure provides NTD developers and corresponding lithography techniques that can overcome resolution, line edge roughness (LER), and sensitivity (RLS) tradeoff barriers particular to extreme ultraviolet (EUV) technologies, thereby achieving high patterning fidelity for advanced technology nodes. An exemplary lithography method includes forming a negative tone resist layer over a workpiece; exposing the negative tone resist layer to EUV radiation; and removing an unexposed portion of the negative tone resist layer in a negative tone developer, thereby forming a patterned negative tone resist layer. The negative tone developer includes an organic solvent having a log P value greater than 1.82. The organic solvent is an ester acetate derivative represented by R1COOR2. R1 and R2 are hydrocarbon chains having four or less carbon atoms. In some implementations, R1, R2, or both R1 and R2 are propyl functional groups, such as n-propyl, isopropyl, or 2-methylpropyl.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yu Liu, Wei-Han Lai, Tzu-Yang Lin, Ming-Hui Weng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10515802
    Abstract: A method may include depositing a mask layer on a substrate using physical vapor deposition, wherein an absolute value of a stress in the mask layer has a first value; and directing a dose of ions into the mask layer, wherein the absolute value of the stress in the mask layer has a second value, less than the first value, after the directing the dose.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: December 24, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Tzu-Yu Liu, Edwin Arevalo, Deven Mittal, Somchintana Norasetthekul, Kyuha Shim, Lauren Liaw, Takaski Shimizu, Nobuyuki Sasaki, Ryuichi Muira, Hiro Ito
  • Patent number: 10468443
    Abstract: A photo diode includes a pixel unit, a photo conversion layer, and a dielectric layer. The pixel unit includes a pair of pixels. The photo conversion layer is above the pixel unit and has a pair of portions, each of which corresponds to a respective one of the pixels. The dielectric layer is between the portions of the photo conversion layer. A method of manufacturing the photo diode is also disclosed.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tzu-Jui Wang, Keng-Yu Chou, Chun-Hao Chuang, Ming-Chieh Hsu, Ren-Jie Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20190326116
    Abstract: A method may include depositing a mask layer on a substrate using physical vapor deposition, wherein an absolute value of a stress in the mask layer has a first value; and directing a dose of ions into the mask layer, wherein the absolute value of the stress in the mask layer has a second value, less than the first value, after the directing the dose.
    Type: Application
    Filed: July 9, 2018
    Publication date: October 24, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Tzu-Yu Liu, Edwin Arevalo, Deven Mittal, Somchintana Norasetthekul, Kyuha Shim, Lauren Liaw, Takaski Shimizu, Nobuyuki Sasaki, Ryuichi Muira, Hiro Ito
  • Publication number: 20190304783
    Abstract: A method may include depositing a carbon layer on a substrate using physical vapor deposition, wherein the carbon layer exhibits compressive stress, and is characterized by a first stress value; and directing a dose of low-mass species into the carbon layer, wherein, after the directing, the carbon layer exhibits a second stress value, less compressive than the first stress value.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 3, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Tzu-Yu Liu, Kyu-HA Shim, Tom Ho Wing Yu, Zhong Qiang Hua, Adolph Miller Allen, Viabhav Soni, Ravi Rajagopalan, Nobuyuki Sasaki
  • Patent number: 10427272
    Abstract: A method of polishing includes polishing a layer of a substrate, monitoring the layer of the substrate with an in-situ monitoring system to generate signal that depends on a thickness of the layer, filtering the signal to generate a filtered signal, determining an adjusted threshold value from an original threshold value and a time delay value representative of time required for filtering the signal, and triggering a polishing endpoint when the filtered signal crosses the adjusted threshold value.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: October 1, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Kun Xu, Kevin Lin, Ingemar Carlsson, Shih-Haur Shen, Tzu-Yu Liu
  • Publication number: 20190237769
    Abstract: A cathode layer and a membrane electrode assembly of a solid oxide fuel cell are provided. The cathode layer consists of a plurality of perovskite crystal films, and the average change rate of linear thermal expansion coefficients of these perovskite crystal films is about 5% to 40% along the thickness direction. The membrane electrode assembly includes the above-mentioned cathode layer, and the linear thermal expansion coefficients of these perovskite crystal films are reduced towards the solid electrolyte layer of the membrane electrode assembly.
    Type: Application
    Filed: January 24, 2019
    Publication date: August 1, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Tzu-Chi Chou, Kuo-Chuang Chiu, Tzu-Yu Liu, Yung-Hsiang Juan, Ying-Hao Chu
  • Patent number: 10354875
    Abstract: A method may include forming a sacrificial mask on a device structure, the sacrificial mask comprising a carbon-based material. The method may further include etching memory structures in exposed regions of the sacrificial mask, implanting an etch-enhancing species into the sacrificial mask, and performing a wet etch to selectively remove the sacrificial mask at etch temperature, less than 350° C.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: July 16, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Ning Zhan, Tzu-Yu Liu, James Cournoyer, Kyu-Ha Shim, Kwangduk Lee, John Lee Klocke, Eric J. Bergman, Terrance Lee, Harry S. Whitesell
  • Publication number: 20190214255
    Abstract: A method may include forming a sacrificial mask on a device structure, the sacrificial mask comprising a carbon-based material. The method may further include etching memory structures in exposed regions of the sacrificial mask, implanting an etch-enhancing species into the sacrificial mask, and performing a wet etch to selectively remove the sacrificial mask at etch temperature, less than 350° C.
    Type: Application
    Filed: April 6, 2018
    Publication date: July 11, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Ning Zhan, Tzu-Yu Liu, James Cournoyer, Kyu-Ha Shim, Kwangduk Lee, John Lee Klocke, Eric J. Bergman, Terrance Lee, Harry S. Whitesell
  • Publication number: 20190134775
    Abstract: A method of controlling polishing includes polishing a substrate at a first polishing station, monitoring the substrate with a first eddy current monitoring system to generate a first signal, determining an ending value of the first signal for an end of polishing of the substrate at the first polishing station, determining a first temperature at the first polishing station, polishing the substrate at a second polishing station, monitoring the substrate with a second eddy current monitoring system to generate a second signal, determining a starting value of the second signal for a start of polishing of the substrate at the second polishing station, determining a gain for the second polishing station based on the ending value, the starting value and the first temperature, and calculating a third signal based on the second signal and the gain.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Inventors: Kun Xu, Shih-Haur Shen, Boguslaw A. Swedek, Ingemar Carlsson, Doyle E. Bennett, Wen-Chiang Tu, Hassan G. Iravani, Tzu-Yu Liu
  • Patent number: 10274443
    Abstract: A urea concentration identification method is provided. By providing an identical sine-wave AC signal to each of the urea concentration identification devices placed in urea solutions of different concentrations, different impedance values are output by the urea concentration identification devices since the urea solutions of different concentrations have different electrical interactions with the electrodes of the urea concentration identification device. Differences of the impedance output by the urea concentration identification device function as a data set for determining the concentration of the urea solution to be determined.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: April 30, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Tzu-Yu Liu, Kuo-Chuang Chiu, Hung Tien, Yeh-Chyang Huang
  • Patent number: 10207386
    Abstract: A method of controlling polishing includes polishing a substrate at a first polishing station, monitoring the substrate with a first eddy current monitoring system to generate a first signal, determining an ending value of the first signal for an end of polishing of the substrate at the first polishing station, determining a first temperature at the first polishing station, polishing the substrate at a second polishing station, monitoring the substrate with a second eddy current monitoring system to generate a second signal, determining a starting value of the second signal for a start of polishing of the substrate at the second polishing station, determining a gain for the second polishing station based on the ending value, the starting value and the first temperature, and calculating a third signal based on the second signal and the gain.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: February 19, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Kun Xu, Shih-Haur Shen, Boguslaw A. Swedek, Ingemar Carlsson, Doyle E. Bennett, Wen-Chiang Tu, Hassan G. Iravani, Tzu-Yu Liu
  • Publication number: 20180203090
    Abstract: A first resistivity value and a correlation function relating thickness of a conductive layer having the first resistivity value to a signal from an in-situ monitoring system are stored. A second resistivity value for a conductive layer on a substrate is received. A sequence of signal values that depend on thickness of the conductive layer is received from an in-situ electromagnetic induction monitoring system that monitors the substrate during polishing. A sequence of thickness values is generated based on the sequence of signal values and the correlation function. For at least some thickness values of the sequence of thickness values adjusted thickness values are generated that compensate for variation between the first resistivity value and the second resistivity value to generate a sequence of adjusted thickness values. A polishing endpoint is detected or an adjustment for a polishing parameter is determined based on the sequence of adjusted thickness values.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 19, 2018
    Inventors: Kun Xu, Ingemar Carlsson, Shih-Haur Shen, Boguslaw A. Swedek, Tzu-Yu Liu
  • Publication number: 20180203089
    Abstract: A first resistivity value and a correlation function relating thickness of a conductive layer having the first resistivity value to a signal from an in-situ monitoring system are stored. A second resistivity value for a conductive layer on a substrate is received. A sequence of signal values that depend on thickness of the conductive layer is received from an in-situ electromagnetic induction monitoring system that monitors the substrate during polishing. A sequence of thickness values is generated based on the sequence of signal values and the correlation function. For at least some thickness values of the sequence of thickness values adjusted thickness values are generated that compensate for variation between the first resistivity value and the second resistivity value to generate a sequence of adjusted thickness values. A polishing endpoint is detected or an adjustment for a polishing parameter is determined based on the sequence of adjusted thickness values.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 19, 2018
    Inventors: Kun Xu, Ingemar Carlsson, Shih-Haur Shen, Boguslaw A. Swedek, Tzu-Yu Liu