Abstract: A micro light emitting diode structure including an epitaxial structure, a first insulating layer and a second insulating layer is provided. The epitaxial structure includes a first type semiconductor layer, a light emitting layer and a second type semiconductor layer. The first type semiconductor layer, the light emitting layer and a first portion of the second type semiconductor layer form a mesa. A second portion of the second type semiconductor layer is recessed relative the mesa to form a mesa surface. The first insulating layer covers from a top surface of the mesa to the mesa surface along a first side surface of the mesa, and exposes the second side surface. The second insulating layer directly covers a second side surface of the second portion, wherein a thickness ratio of the first insulating layer to the second insulating layer is between 10 and 50.

Abstract: A method of maximizing power efficiency for a power amplifier system comprises obtaining a power supply voltage; determining a first voltage level sufficient for a power amplifier of the power amplifier system to output an output power; determining a second voltage level lower than the first voltage level; determining whether the power amplifier is activated, to generate a determination result; determining to convert the power supply voltage into a supply voltage with the first voltage level or the second voltage level according to the determination result; and supplying the power amplifier with the supply voltage.

Abstract: A circuit for implementing an operational transconductance amplifier (OTA) based on telescopic topology, wherein cascode transistors of the operational transconductance amplifier (OTA) are self-biased without using additional biasing circuitry, which not only reduces power consumption but also achieves high gain without extra current, and each cascode stage of the OTA has a pair of transistors so that the swing of the output differential signals of the OTA can be completely symmetrical so as to benefit second-order harmonic rejection, CMRR and PSRR.

Abstract: A single chip for generating multiple differential signals and loop-through signals according to a single-ended RF signal inputted to the single chip, wherein delays between different channels of the multiple differential signals and loop-through signals can be minimized for supporting picture-in-picture applications; in addition, the single chip can integrate a power detector and an AGC circuit for controlling the gain of an LNA inside the single chip, and the gain of the LNA can be outputted from the single chip for different usages.

Abstract: A dynamic current correlating circuit is disclosed. The current correlating circuit includes a reset circuit, a first current generating circuit and a second current generating circuit. The reset circuit executes a discharging procedure during a first time interval and executes a charging procedure during a second time interval. The first current generating circuit is electrically connected to the reset circuit. The first current generating circuit generates a first sub-current and a second sub-current during a third time interval according to a first input voltage and a second input voltage and generates a first current after the third time interval. The second current generating circuit is electrically connected to the reset circuit. The second current generating circuit generates a second current according to the first input voltage and the second input voltage after the third time interval.

Abstract: A dynamic current correlating circuit is disclosed. The current correlating circuit includes a reset circuit, a first current generating circuit and a second current generating circuit. The reset circuit executes a discharging procedure during a first time interval and executes a charging procedure during a second time interval. The first current generating circuit is electrically connected to the reset circuit. The first current generating circuit generates a first sub-current and a second sub-current during a third time interval according to a first input voltage and a second input voltage and generates a first current after the third time interval. The second current generating circuit is electrically connected to the reset circuit. The second current generating circuit generates a second current according to the first input voltage and the second input voltage after the third time interval.

Abstract: An operational transconductance amplifier includes a fully-differential amplifying circuit, a bias driving circuit, and a common mode feedback circuit. The fully-differential amplifying circuit is configured for receiving a differential input voltage and providing a differential output voltage. The fully-differential amplifying circuit includes a plurality of diffusor-differential-pair circuits. The bias driving circuit is configured for providing at least one first bias current to drive the fully-differential amplifying circuit and adjust the transconductance of the transconductance amplifier. The common mode feedback circuit is configured for stabilizing the differential output voltage. An operational transconductance amplifier-capacitor (OTA-C) filter and a high order filter are disclosed herein as well.

Abstract: An operational transconductance amplifier includes a cascode differential-pair amplifying circuit, a bias driving circuit, and a common mode feedback circuit. The cascode differential-pair amplifying circuit is configured for receiving a differential input voltage and for providing a differential output voltage. The bias driving circuit is configured for providing a first bias current to drive the cascode differential-pair amplifying circuit and for adjusting the transconductance of the transconductance amplifier. The bias driving circuit includes a first floating-gate transistor. The first floating-gate transistor is configured for adjusting the first bias current. The common mode feedback circuit is configured for adjusting a second bias current of the cascode differential-pair amplifying circuit according to the differential output voltage so that the differential output voltage is stabilized.

Abstract: A serial-parallel interface circuit with nonvolatile memories is provided. A control module generates a plurality of control signals, wherein the control signals include readout and write-in control signals and memory programming control signals. An input terminal receives a plurality of digital data from external. The digital data are transmitted to the input terminal serially. Memory modules are coupled to the input terminal and receive the control signals from the control module. The input terminal transmits the digital data to the memory modules. One of the memory modules includes a memory unit, and the memory unit stores or transmits one bit of the digital data based on a high voltage control signal and a memory control signal. A plurality of output signal lines are respectively coupled to the memory modules. The memory unit transmits the one bit of the digital data to one of the output signal lines.

Abstract: An operational transconductance amplifier includes a cascode differential-pair amplifying circuit, a bias driving circuit, and a common mode feedback circuit. The cascode differential-pair amplifying circuit is configured for receiving a differential input voltage and for providing a differential output voltage. The bias driving circuit is configured for providing a first bias current to drive the cascode differential-pair amplifying circuit and for adjusting the transconductance of the transconductance amplifier. The bias driving circuit includes a first floating-gate transistor. The first floating-gate transistor is configured for adjusting the first bias current. The common mode feedback circuit is configured for adjusting a second bias current of the cascode differential-pair amplifying circuit according to the differential output voltage so that the differential output voltage is stabilized.

Abstract: An operational transconductance amplifier includes a fully-differential amplifying circuit, a bias driving circuit, and a common mode feedback circuit. The fully-differential amplifying circuit is configured for receiving a differential input voltage and providing a differential output voltage. The fully-differential amplifying circuit includes a plurality of diffusor-differential-pair circuits. The bias driving circuit is configured for providing at least one first bias current to drive the fully-differential amplifying circuit and adjust the transconductance of the transconductance amplifier. The common mode feedback circuit is configured for stabilizing the differential output voltage. An operational transconductance amplifier-capacitor (OTA-C) filter and a high order filter are disclosed herein as well.

Abstract: A serial-parallel interface circuit with nonvolatile memories is provided. A control module generates a plurality of control signals, wherein the control signals include readout and write-in control signals and memory programming control signals. An input terminal receives a plurality of digital data from external. The digital data are transmitted to the input terminal serially. Memory modules are coupled to the input terminal and receive the control signals from the control module. The input terminal transmits the digital data to the memory modules. One of the memory modules includes a memory unit, and the memory unit stores or transmits one bit of the digital data based on a high voltage control signal and a memory control signal. A plurality of output signal lines are respectively coupled to the memory modules. The memory unit transmits the one bit of the digital data to one of the output signal lines.

Abstract: A compact disc (CD) feeding mechanism includes a base internally defining a moving passage, and a CD inlet and a CD outlet communicating with an upper and a lower end of the moving passage, respectively, and having a first and a second supporting wall spaced by a shifting path and radially projected into a left side of the CD inlet, an overall length extending along the two supporting walls and the shifting path being larger than one half of the outer circumference of a CD, so that a plurality of CDs may be stacked on the two supporting walls; a driving unit mounted below the base and electrically connected to an external power supply; and a shifting unit including a shifting section driven by the driving unit to shift a lowest one of the stacked CDs out of the supporting walls into the moving passage to the CD outlet.