Abstract: The present invention discloses a USB3.0 clock frequency generation device without crystal oscillator, that is, the crystal oscillator used in the USB3.0 device (or apparatus) is removed and replaced with an oscillator circuit module in the present invention, in which a simple circuit module is added to the controller circuit of the USB3.0 device to provide accurate and proper timing signals needed. The oscillator circuit module includes an oscillator block, a frequency divider block, a delta-sigma modulator block, and a preset number block.

Abstract: The present invention is a low-ripple power supply comprising a clock generator, a plurality of charge pump modules, and an adder unit. The low-ripple power supply inputs each of a plurality of clock signals generated by the clock generator into each of the plurality of charge pump modules. Since each of the plurality of charge pump modules sends the inputted corresponding clock signal into two paths to be inputted into the first and the second charge pump, respectively, and the corresponding clock signal inputted into the second charge pump undergoes an inversion by the inverter, by adding the first voltage outputted by the first charge pump and the second voltage outputted by the second charge pump, the ripples may be eliminated; finally, the adder unit adds the voltages outputted by each of the plurality of charge pump modules to yield a low-ripple DC voltage.

Abstract: The present invention discloses a USB3.0 clock frequency generation device without crystal oscillator, that is, the crystal oscillator used in the USB3.0 device (or apparatus) is removed and replaced with an oscillator circuit module in the present invention, in which a simple circuit module is added to the controller circuit of the USB3.0 device to provide accurate and proper timing signals needed. The oscillator circuit module includes an oscillator block, a frequency divider block, a delta-sigma modulator block, and a preset number block.

Abstract: An oversampling data recovery circuit for a receiver comprises a plurality of sampling circuits for sampling an input data upon a plurality of clocks to generate a plurality of sample data, respectively, an edge detector for determining an edge of the input data by monitoring the plurality of sample data, and a state machine for selecting one from the plurality of sample data as an output data of the oversampling data recovery circuit according to the edge of the input data, such that the receiver will have an optimum timing margin.

Abstract: A bandgap voltage reference circuit includes an operational amplifier, a first transistor, a second transistor, a third transistor, a first resistor, a second resistor, a first diode, a second diode, and a divider. The first transistor, the second transistor, and the third transistor form current mirrors. The reference current of the current mirrors is generated according to the first diode, the second diode, and the first resistor. The reference voltage of the voltage reference circuit is output from the first end of the second resistor. The divider is coupled to the second end of the second resistor so that the reference voltage of the voltage reference circuit can be reduced.

Abstract: A passive equalizer with negative impedance to increase a gain includes a first RC loop, a second RC loop, a cascade RL circuit and a cross-coupled inverter unit. Each of the first and the second RC loops includes a first resistor, a second resistor connected in series to the first resistor at a node to thereby form a resistor series, and a capacitor connected in parallel to the resistor series. The cascade RL circuit is connected between the RC loops and includes a fifth resistor, a sixth resistor and an inductor connected between the fifth resistor and the sixth resistor. The cross-coupled inverter unit is connected in parallel to the RL circuit and connected between the RC loops for using the feature of negative impedance to obtain an excellent high-frequency gain.

Abstract: A passive equalizer with negative impedance to increase a gain includes a first RC loop, a second RC loop, a cascade RL circuit and a cross-coupled inverter unit. Each of the first and the second RC loops includes a first resistor, a second resistor connected in series to the first resistor at a node to thereby form a resistor series, and a capacitor connected in parallel to the resistor series. The cascade RL circuit is connected between the RC loops and includes a fifth resistor, a sixth resistor and an inductor connected between the fifth resistor and the sixth resistor. The cross-coupled inverter unit is connected in parallel to the RL circuit and connected between the RC loops for using the feature of negative impedance to obtain an excellent high-frequency gain.

Abstract: A bandgap voltage reference circuit includes an operational amplifier, a first transistor, a second transistor, a third transistor, a first resistor, a second resistor, a first diode, a second diode, and a divider. The first transistor, the second transistor, and the third transistor form current mirrors. The reference current of the current mirrors is generated according to the first diode, the second diode, and the first resistor. The reference voltage of the voltage reference circuit is output from the first end of the second resistor. The divider is coupled to the second end of the second resistor so that the reference voltage of the voltage reference circuit can be reduced.

Abstract: An oversampling data recovery circuit for a receiver comprises a plurality of sampling circuits for sampling an input data upon a plurality of clocks to generate a plurality of sample data, respectively, an edge detector for determining an edge of the input data by monitoring the plurality of sample data, and a state machine for selecting one from the plurality of sample data as an output data of the oversampling data recovery circuit according to the edge of the input data, such that the receiver will have an optimum timing margin.

Abstract: A method for sampling data is disclosed. The method includes providing a first data and a second data, detecting a phase of the first data by a first clock, and sampling the second data by an inverted signal of the first clock.