Abstract: The present disclosure relates to methods and apparatus for graphics processing. In some aspects, multiple processing units can be in a graphics processing pipeline of a GPU. The apparatus can also group the multiple processing units into one or more processing unit clusters. In some aspects, each of the one or more processing unit clusters can correspond to one or more context registers. Additionally, the apparatus can determine one or more context states of the one or more context registers in each of the one or more processing unit clusters. Also, the apparatus can implement one or more execution counters corresponding to at least one of the one or more processing unit clusters in the graphics processing pipeline, where each of the one or more execution counters includes an execution value.

Abstract: A method, an apparatus, and a computer-readable medium may be configured to perform a binning pass for a first frame. The apparatus may be configured to perform a rendering pass for the first frame in parallel with the binning pass. The apparatus may be configured to enhance efficiency in performing a binning pass and a rendering pass for tile-based rendering, such that the binning pass and rendering pass are performed concurrently. The apparatus may be configured to perform the binning pass using a first hardware pipeline, and may be configured to perform the rendering pass using a second hardware pipeline.

Abstract: In accordance with the teachings described herein, systems and methods are provided for advanced execution of branch instructions in a microprocessor pipeline. In one embodiment, a branch instruction of an assembly language program code is executed that includes (i) a condition operand, (ii) a branch destination operand, and (iii) a program count operand. It is determined whether a current program count matches a stored program count operand. After determining that a condition was met when the branch instruction was executed, and in response to determining that the current program count matches the stored program count operand, a destination instruction specified by the stored branch destination operand is fetched.

Abstract: Methods and systems for using a video data compression algorithm with parallel processing capability are provided. AC and DC coefficients associated with blocks of the video data, along with quantization errors, may be encoded using a variable length code. The quantization errors may be encoded using a scheme that assigns priorities to the quantization errors based on the position of their associated AC and/or DC coefficients in a block of the video data. The quantization errors may be appended to a bitstream in an order based on these priorities that enables parallel coding of the quantization errors and AC and DC coefficients in each block of video data. Data packing schemes may also be applied to the coded data to maximize the use of bandwidth resources in encoding and/or decoding.

Abstract: Embodiments of the present invention provide graphic processing techniques and configurations including an apparatus comprising a storage medium having stored therein a table comprising information about respective positions and sizes of a number of rectangular blocks, the rectangular blocks to substantially form at least one plane having an arbitrary shape object, and at least one overlay engine operatively coupled with the table and associated with the at least one plane to request the information about the respective positions and the sizes of the number of rectangular blocks to provide graphics overlay of the arbitrary shape object. Other embodiments may be described and/or claimed.

Abstract: Methods and systems for using a video data compression algorithm with parallel processing capability are provided. AC and DC coefficients associated with blocks of the video data, along with quantization errors, may be encoded using a variable length code. The quantization errors may be encoded using a scheme that assigns priorities to the quantization errors based on the position of their associated AC and/or DC coefficients in a block of the video data. The quantization errors may be appended to a bitstream in an order based on these priorities that enables parallel coding of the quantization errors and AC and DC coefficients in each block of video data. Data packing schemes may also be applied to the coded data to maximize the use of bandwidth resources in encoding and/or decoding.

Abstract: In one embodiment the present invention includes a microprocessor that has a pipeline circuit, a branch circuit, and a control circuit. The pipeline circuit pipelines instructions for the microprocessor. The branch circuit is coupled to the pipeline circuit and operates to store branch information. The control circuit is coupled to the pipeline circuit and the branch circuit. The control circuit stores a first branch information from the pipeline circuit to the branch circuit when a first condition is met. The control circuit retrieves a second branch information from the branch stack circuit to the pipeline circuit when a second condition is met. In this manner, the need for dedicated pipeline flush circuitry is avoided.