Abstract: A method, image processing system, and computer-readable recording medium for item defect inspection are provided. The method is as follows. A test image and a reference image of a test item are received. A test block and a corresponding reference block are obtained from the test image and the reference image to generate a test block image and a reference block image. The test block image and the reference block image are respectively partitioned into multiple sub-blocks. All interfering sub-blocks are identified and filtered out from the test block image and the reference block image, and a shift calibration parameter is obtained accordingly. The test block in the test image is calibrated based on the shift calibration parameter to generate a calibrated test block image. The calibrated test block image and the reference block image are compared to obtain defect information of the test item corresponding to the test block.

Abstract: A method, image processing system, and computer-readable recording medium for item defect inspection are provided. The method is as follows. A test image and a reference image of a test item are received. A test block and a corresponding reference block are obtained from the test image and the reference image to generate a test block image and a reference block image. The test block image and the reference block image are respectively partitioned into multiple sub-blocks. All interfering sub-blocks are identified and filtered out from the test block image and the reference block image, and a shift calibration parameter is obtained accordingly. The test block in the test image is calibrated based on the shift calibration parameter to generate a calibrated test block image. The calibrated test block image and the reference block image are compared to obtain defect information of the test item corresponding to the test block.

Abstract: A method of manufacturing a non-volatile memory is provided. A substrate including a first region and a second region is provided. A first patterning process is performed to the first region, so as to form a plurality of gate stack structures in the first region. Afterwards, a first sidewall oxide layer is formed to cover sidewalls and an upper surface of each gate stack structure, and a protection layer is then formed on the first sidewall oxide layer. Next, an ion implantation process is performed to the second region, and a second patterning process is performed to the second region so as to form a plurality of gate structures. Then, a second sidewall oxide layer covering sidewalls of each gate structure is formed.

Abstract: A method of making a flash memory includes providing a substrate. Then, a first insulating layer, a first conductive layer and a second insulating layer are formed to cover the substrate. Later, a first trench is formed in the first conductive layer and the second insulating layer. After that, a second conductive layer and a mask layer are formed to cover the second insulating layer, and the second conductive layer fills up the first trench. Then, the mask layer are patterned to form patterned mask layers. Subsequently, a spacer is formed on the sidewall of the patterned mask layer. Then, an etching process is carried out by using the patterned mask layers and the spacer as a mask so as to form a first gate structure and a second gate structure.

Abstract: A non-volatile memory cell, a NAND-type non-volatile memory, and a method of manufacturing the same are provided. The method of manufacturing the non-volatile memory cell includes the following steps. An insulating layer, a first conductive layer, an inter-gate insulating layer, a second conductive layer, and a hard mask layer are formed on a substrate in order. The hard mask layer, the second conductive layer, the inter-gate insulating layer, and the first conductive layer are patterned to form a stacked gate structure. The insulating layer on the substrate at two sides of the stacked gate structure is removed until the surface of the substrate is exposed. A portion of the substrate at two sides of the stacked gate structure is removed to form two recesses in the substrate, and each of the recesses is extended below the stacked gate structure. A source/drain region is formed in the substrate below the recesses.

Abstract: A method of manufacturing a non-volatile memory is provided. A substrate including a first region and a second region is provided. A first patterning process is performed to the first region, so as to form a plurality of gate stack structures in the first region. Afterwards, a first sidewall oxide layer is formed to cover sidewalls and an upper surface of each gate stack structure, and a protection layer is then formed on the first sidewall oxide layer. Next, an ion implantation process is performed to the second region, and a second patterning process is performed to the second region so as to form a plurality of gate structures. Then, a second sidewall oxide layer covering sidewalls of each gate structure is formed.

Abstract: A non-volatile memory including a substrate, a first stacked structure, a second stacked structure, a fifth conductive layer, a first doped region, and a second doped region is provided. The first stacked structure includes a first conductive layer and a second conductive layer stacked on the substrate in order and isolated from each other. The second stacked structure is separately disposed from the first stacked structure and includes a third conductive layer and a fourth conductive layer stacked on the substrate in order and connected to each other. The fifth conductive layer is disposed on the substrate at one side of the first stacked structure away from the second stacked structure. The first doped region is disposed in the substrate below the fifth conductive layer. The second doped region is disposed in the substrate at one side of the second stacked structure away from the first stacked structure.

Abstract: A method of making a flash memory includes providing a substrate. Then, a first insulating layer, a first conductive layer and a second insulating layer are formed to cover the substrate. Later, a first trench is formed in the first conductive layer and the second insulating layer. After that, a second conductive layer and a mask layer are formed to cover the second insulating layer, and the second conductive layer fills up the first trench. Then, the mask layer are patterned to form patterned mask layers. Subsequently, a spacer is formed on the sidewall of the patterned mask layer. Then, an etching process is carried out by using the patterned mask layers and the spacer as a mask so as to form a first gate structure and a second gate structure.

Abstract: A hemispherical silicon grain (HSG) process is described. A doped poly-Si layer is formed on a substrate, and then an oxidative gas is used to oxidize the surface of the doped poly-Si layer to form an oxide layer. An a-Si layer is then formed on the oxide layer, and the a-Si layer is converted into HSG.

Abstract: A method of monitoring the conditions during chemical vapor deposition. First, a first substrate is provided. A first oxide layer is formed over the first substrate and then a first silicon nitride layer is deposited over the first oxide layer under a set of depositing conditions. The first silicon nitride layer is removed so that the remaining first oxide layer can serve as a first measuring oxide layer. The interface trap density of the first measuring oxide layer is measured to obtain a first interface trap density. A second substrate is provided. A second oxide layer is formed over the second substrate. After setting the depositing conditions identical to the set of depositing conditions for depositing the first silicon nitride layer over the first substrate, a second silicon nitride layer is deposited over the second oxide layer. The second silicon nitride layer is performed under an actual set of depositing conditions.

Abstract: A method of increasing the selectivity of silicon nitride deposition. A substrate is provided. A silicon oxide layer is formed over a portion of the substrate. Ammonia NH3 is passed over the silicon oxide layer and the substrate surface for a definite period to perform a surface treatment. Silicon nitride is subsequently deposited over the substrate and the silicon oxide layer.