Patents by Inventor Tzung-Yu Hung

Tzung-Yu Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7884028
    Abstract: A method of removing material layer is disclosed. First, a semiconductor substrate is fixed on a rotating platform, where a remnant material layer is included on the surface of the semiconductor substrate. Afterward, an etching process is carried out. In the etching process, the rotating platform is rotated, and an etching solution is sprayed from a center region and a side region of the rotating platform toward the semiconductor substrate until the material layer is removed. Since the semiconductor substrate is etched by the etching solution sprayed from both the center region and the side region of the rotating platform, the etching uniformity of the semiconductor substrate is improved.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: February 8, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Wei Chen, Chun-Chieh Chang, Tzung-Yu Hung, Yu-Lan Chang, Chao-Ching Hsieh
  • Patent number: 7785972
    Abstract: A method of making a transistor device having silicided source/drain is provided. A gate electrode is formed on a substrate with a gate dielectric layer therebetween. A spacer is formed on sidewalls of the gate electrode. A source/drain is implanted into the substrate. A pre-amorphization implant (PAI) is performed to form an amorphized layer on the source/drain. A post-PAI annealing process is performed to repair defects formed during the PAI process. A metal silicide layer is then formed from the amorphized layer.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: August 31, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Wei Chen, Tzung-Yu Hung, Chun-Chieh Chang
  • Patent number: 7649263
    Abstract: A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a protection layer. The refractory metal salicide layer is disposed over the silicon-containing conductive layer. The protection layer is disposed over the refractory metal salicide layer. Another semiconductor device including at least one conductive structure is also provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal alloy salicide layer and a protection layer. The refractory metal alloy salicide layer is disposed over the silicon-containing conductive layer. The refractory metal alloy salicide layer is formed from a reaction of silicon of the silicon-containing conductive layer and a refractory metal alloy layer which includes a first refractory metal and a second refractory metal. The protection layer is disposed over the refractory metal alloy salicide layer.
    Type: Grant
    Filed: November 23, 2007
    Date of Patent: January 19, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Yiing Chiang, Yi-Wei Chen, Tzung-Yu Hung
  • Patent number: 7595264
    Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a refractory metal alloy layer over a silicon-containing conductive layer. The refractory metal alloy layer is constituted of a first refractory metal and a second refractory metal. Thereafter, a cap layer is formed on the refractory metal alloy layer. A thermal process is performed so that the refractory metal alloy layer reacts with silicon of the silicon-containing conductive layer to form a refractory metal alloy salicide layer. Afterwards, an etch process with an etch solution is performed to removes the cap layer and the refractory metal alloy layer which has not been reacted and to form a protection layer on the refractory metal alloy salicide layer.
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: September 29, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Yiing Chiang, Yi-Wei Chen, Tzung-Yu Hung
  • Patent number: 7572722
    Abstract: A semiconductor device having nickel silicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the doped regions disposed there under. Thereafter, the unreacted nickel layer is removed, and a second rapid thermal process is performed to form a semiconductor device having nickel silicide. The second rapid thermal process is a spike anneal process whose process temperature is between 400 and 600° C.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: August 11, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Wei Chen, Chao-Ching Hsieh, Yi-Yiing Chiang, Tzung-Yu Hung, Yu-Lan Chang, Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen
  • Patent number: 7553762
    Abstract: The invention provides a method for forming a metal silicide layer. The method comprises steps of providing a substrate and forming a nickel-noble metal layer over the substrate. A grain boundary sealing layer is formed on the nickel-noble metal layer and then an oxygen diffusion barrier layer is formed on the grain boundary sealing layer. Thereafter, a rapid thermal process is performed to transform a portion of the nickel-noble metal layer into a metal silicide layer. Finally, the oxygen diffusion barrier layer, the grain boundary sealing layer and the rest portion of the nickel-noble metal layer are removed.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: June 30, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Tzung-Yu Hung, Chun-Chieh Chang, Chao-Ching Hsieh, Yu-Lan Chang, Yi-Wei Chen
  • Patent number: 7482668
    Abstract: A semiconductor device is provided. A transistor is formed on a substrate, and a metal silicide layer is formed on the surface of a gate conductor layer and a source/drain region. Next, a surface treatment process is performed to selectively form a protection layer on the surface of the metal silicide layer. Then, a spacer of the transistor is partially removed using the protection layer as a mask, so as to reduce the width of the spacer. Then, a stress layer is formed on the substrate.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: January 27, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Chao-Ching Hsieh, Chun-Chieh Chang, Tzung-Yu Hung
  • Publication number: 20080254640
    Abstract: A method of removing material layer is disclosed. First, a semiconductor substrate is fixed on a rotating platform, where a remnant material layer is included on the surface of the semiconductor substrate. Afterward, an etching process is carried out. In the etching process, the rotating platform is rotated, and an etching solution is sprayed from a center region and a side region of the rotating platform toward the semiconductor substrate until the material layer is removed. Since the semiconductor substrate is etched by the etching solution sprayed from both the center region and the side region of the rotating platform, the etching uniformity of the semiconductor substrate is improved.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 16, 2008
    Inventors: Yi-Wei Chen, Chun-Chieh Chang, Tzung-Yu Hung, Yu-Lan Chang, Chao-Ching Hsieh
  • Publication number: 20080224232
    Abstract: A silicidation process for a MOS transistor and a resulting transistor structure are described. The MOS transistor includes a silicon substrate, a gate dielectric layer, a silicon gate, a cap layer on the silicon gate, a spacer on the sidewalls of the silicon gate and the cap layer, and S/D regions in the substrate beside the silicon gate. The process includes forming a metal silicide layer on the S/D regions, utilizing plasma of a reactive gas to react a surface layer of the metal silicide layer into a passivation layer, removing the cap layer and then reacting the silicon gate into a fully silicided gate.
    Type: Application
    Filed: March 16, 2007
    Publication date: September 18, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Ching Hsieh, Yu-Lan Chang, Chien-Chung Huang, Tzung-Yu Hung, Chun-Chieh Chang, Yi-Wei Chen
  • Publication number: 20080194100
    Abstract: The invention provides a method for forming a metal silicide layer. The method comprises steps of providing a substrate and forming a nickel-noble metal layer over the substrate. A grain boundary sealing layer is formed on the nickel-noble metal layer and then an oxygen diffusion barrier layer is formed on the grain boundary sealing layer. Thereafter, a rapid thermal process is performed to transform a portion of the nickel-noble metal layer into a metal silicide layer. Finally, the oxygen diffusion barrier layer, the grain boundary sealing layer and the rest portion of the nickel-noble metal layer are removed.
    Type: Application
    Filed: February 9, 2007
    Publication date: August 14, 2008
    Applicant: United Microelectronics Corp.
    Inventors: Tzung-Yu Hung, Chun-Chieh Chang, Chao-Ching Hsieh, Yu-Lan Chang, Yi-Wei Chen
  • Publication number: 20080171449
    Abstract: A method for cleaning suicide includes providing a substrate having at least an intergraded silicide and residues, sequentially performing an ammonia hydrogen peroxide (APM) mixture cleaning process and a vaporized hydrochloric acid-hydrogen peroxide mixture (HPM) cleaning process to remove the residues, and performing a sulfuric acid-hydrogen peroxide mixture (SPM) cleaning process to remove residuals of the vaporized HPM cleaning process.
    Type: Application
    Filed: January 15, 2007
    Publication date: July 17, 2008
    Inventors: Chao-Ching Hsieh, Tzung-Yu Hung, Chun-Chieh Chang, Yi-Wei Chen, Yu-Lan Chang
  • Patent number: 7390754
    Abstract: A method of stripping a remnant metal is disclosed. The remnant metal is formed on a transitional silicide of a silicon substrate. Firstly, a surface oxidation process is performed on the transitional silicide, so as to form a protective layer on the transitional silicide. Then, a HPM stripping process is performed on the silicon substrate in order to strip the remnant metal.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: June 24, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Chieh Chang, Tzung-Yu Hung, Chao-Ching Hsieh, Yi-Wei Chen, Yu-Lan Chang
  • Patent number: 7390729
    Abstract: A method of fabricating semiconductor device is provided. A transistor is formed on a substrate, and a metal silicide layer is formed on the surface of a gate conductor layer and a source/drain region. Next, a surface treatment process is performed to selectively form a protection layer on the surface of the metal silicide layer. Then, a spacer of the transistor is partially removed using the protection layer as a mask, so as to reduce the width of the spacer. Then, a stress layer is formed on the substrate.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: June 24, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Chao-Ching Hsieh, Chun-Chieh Chang, Tzung-Yu Hung
  • Patent number: 7385294
    Abstract: A semiconductor device having nickel silicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the doped regions disposed thereunder. Thereafter, the unreacted nickel layer is removed, and a second rapid thermal process is performed to form a semiconductor device having nickel silicide. The second rapid thermal process is a spike anneal process whose process temperature is between 400 and 600° C.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: June 10, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Wei Chen, Chao-Ching Hsieh, Yi-Yiing Chiang, Tzung-Yu Hung, Yu-Lan Chang, Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen
  • Publication number: 20080132063
    Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a refractory metal alloy layer over a silicon-containing conductive layer. The refractory metal alloy layer is constituted of a first refractory metal and a second refractory metal. Thereafter, a cap layer is formed on the refractory metal alloy layer. A thermal process is performed so that the refractory metal alloy layer reacts with silicon of the silicon-containing conductive layer to form a refractory metal alloy salicide layer. Afterwards, an etch process with an etch solution is performed to removes the cap layer and the refractory metal alloy layer which has not been reacted and to form a protection layer on the refractory metal alloy salicide layer.
    Type: Application
    Filed: January 21, 2008
    Publication date: June 5, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Yiing Chiang, Yi-Wei Chen, Tzung-Yu Hung
  • Publication number: 20080073727
    Abstract: A semiconductor device is provided. A transistor is formed on a substrate, and a metal silicide layer is formed on the surface of a gate conductor layer and a source/drain region. Next, a surface treatment process is performed to selectively form a protection layer on the surface of the metal silicide layer. Then, a spacer of the transistor is partially removed using the protection layer as a mask, so as to reduce the width of the spacer. Then, a stress layer is formed on the substrate.
    Type: Application
    Filed: July 27, 2007
    Publication date: March 27, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Ching Hsieh, Chun-Chieh Chang, Tzung-Yu Hung
  • Publication number: 20080076213
    Abstract: A method of fabricating semiconductor device is provided. A transistor is formed on a substrate, and a metal suicide layer is formed on the surface of a gate conductor layer and a source/drain region. Next, a surface treatment process is performed to selectively form a protection layer on the surface of the metal silicide layer. Then, a spacer of the transistor is partially removed using the protection layer as a mask, so as to reduce the width of the spacer. Then, a stress layer is formed on the substrate.
    Type: Application
    Filed: September 21, 2006
    Publication date: March 27, 2008
    Inventors: Chao-Ching Hsieh, Chun-Chieh Chang, Tzung-Yu Hung
  • Publication number: 20080067684
    Abstract: A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a protection layer. The refractory metal salicide layer is disposed over the silicon-containing conductive layer. The protection layer is disposed over the refractory metal salicide layer. Another semiconductor device including at least one conductive structure is also provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal alloy salicide layer and a protection layer. The refractory metal alloy salicide layer is disposed over the silicon-containing conductive layer. The refractory metal alloy salicide layer is formed from a reaction of silicon of the silicon-containing conductive layer and a refractory metal alloy layer which includes a first refractory metal and a second refractory metal. The protection layer is disposed over the refractory metal alloy salicide layer.
    Type: Application
    Filed: November 23, 2007
    Publication date: March 20, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Yiing Chiang, Yi-Wei Chen, Tzung-Yu Hung
  • Patent number: 7344978
    Abstract: A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a protection layer. The refractory metal salicide layer is disposed over the silicon-containing conductive layer. The protection layer is disposed over the refractory metal salicide layer. Another semiconductor device including at least one conductive structure is also provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal alloy salicide layer and a protection layer. The refractory metal alloy salicide layer is disposed over the silicon-containing conductive layer. The refractory metal alloy salicide layer is formed from a reaction of silicon of the silicon-containing conductive layer and a refractory metal alloy layer which includes a first refractory metal and a second refractory metal. The protection layer is disposed over the refractory metal alloy salicide layer.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: March 18, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Yiing Chiang, Yi-Wei Chen, Tzung-Yu Hung
  • Publication number: 20080038887
    Abstract: A method of making a transistor device having silicided source/drain is provided. A gate electrode is formed on a substrate with a gate dielectric layer therebetween. A spacer is formed on sidewalls of the gate electrode. A source/drain is implanted into the substrate. A pre-amorphization implant (PAI) is performed to form an amorphized layer on the source/drain. A post-PAI annealing process is performed to repair defects formed during the PAI process. A metal silicide layer is then formed from the amorphized layer.
    Type: Application
    Filed: August 8, 2006
    Publication date: February 14, 2008
    Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Wei Chen, Tzung-Yu Hung, Chun-Chieh Chang