Patents by Inventor Tzy-Kuang LEE
Tzy-Kuang LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961762Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.Type: GrantFiled: June 30, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Song-Bor Lee, Wen-Hsiung Lu, Po-Hao Tsai, Wen-Che Chang
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Publication number: 20230378052Abstract: A method includes depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant, forming a capacitor over the first passivation layer, and depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line over and electrically connecting to the capacitor, depositing a third passivation layer over the redistribution line, and forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.Type: ApplicationFiled: August 3, 2023Publication date: November 23, 2023Inventors: Chia-Ming Huang, Ming-Da Cheng, Songbor Lee, Jung-You Chen, Ching-Hua Kuan, Tzy-Kuang Lee
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Publication number: 20230307366Abstract: Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.Type: ApplicationFiled: June 5, 2023Publication date: September 28, 2023Inventors: Wen-Chun Wang, Tzy-Kuang Lee, Chih-Hsien Lin, Ching-Hung Kao, Yen-Yu Chen
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Publication number: 20230299124Abstract: A method of forming a capacitor is disclosed. The method includes forming a portion of a metallization layer on a substrate, forming a via layer on the substrate, and forming a first electrode between the metallization layer and the via layer, where the first electrode is electrically connected to the metallization layer. The method also includes forming a second electrode between the metallization layer and the via layer, where the second electrode is electrically connected to the via layer, and forming a dielectric layer between the first electrode and the second electrode, where the first electrode is not electrically connected to any other conductors other than through the metallization layer, and where the second electrode is not electrically connected to any conductors other than through the via layer.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Inventors: Pei-Jen Wang, Ching-Hung Kao, Tzy-Kuang Lee, Meng-Chang Ho, Kun-Mao Wu
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Publication number: 20230253204Abstract: A semiconductor device includes a semiconductor substrate, a plurality of isolation structures on the semiconductor substrate, and a plurality of blocking structures disposed directly over the isolation structures. The blocking structures have a lower reflectivity than the isolation structures.Type: ApplicationFiled: April 3, 2023Publication date: August 10, 2023Inventors: Yu-Hsuan YANG, Tzy-Kuang LEE, Chia Ying LIN, Wen Han HUNG
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Patent number: 11670594Abstract: Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.Type: GrantFiled: May 5, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Chun Wang, Tzy-Kuang Lee, Chih-Hsien Lin, Ching-Hung Kao, Yen-Yu Chen
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Patent number: 11621165Abstract: A semiconductor device includes a semiconductor substrate, a plurality of isolation structures on the semiconductor substrate, and a plurality of blocking structures disposed directly over the isolation structures. The blocking structures have a lower reflectivity than the isolation structures.Type: GrantFiled: February 22, 2021Date of Patent: April 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Hsuan Yang, Wen Han Hung, Tzy-Kuang Lee, Chia Ying Lin
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Publication number: 20230052604Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device may include a substrate, a first via, a first pad, a second pad, and a first passivation layer. The first pad may be over the substrate. The second pad may be over the substrate. The second pad may be parallel to the first pad. The first passivation layer may surround the first pad and the second pad. The first passivation layer may include a first part on the first pad. The first passivation layer may include a second part on the second pad. A thickness of the first part of the first passivation layer may exceed a height of the first pad. A thickness of the second part of the first passivation layer may exceed a height of the second pad.Type: ApplicationFiled: January 12, 2022Publication date: February 16, 2023Inventors: Ching-Hung Kao, Kuei-Yu Deng, Tzy-Kuang Lee
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Publication number: 20220384259Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Hao Chun Liu, Po-Hao Tsai, Chih-Hsien Lin, Ching-Wen Hsiao
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Publication number: 20220336276Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Song-Bor Lee, Wen-Hsiung Lu, Po-Hao Tsai, Wen-Che Chang
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Patent number: 11450567Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.Type: GrantFiled: October 30, 2020Date of Patent: September 20, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Song-Bor Lee, Wen-Hsiung Lu, Po-Hao Tsai, Wen-Che Chang
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Publication number: 20220223536Abstract: Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.Type: ApplicationFiled: May 5, 2021Publication date: July 14, 2022Inventors: Wen-Chun Wang, Tzy-Kuang Lee, Chih-Hsien Lin, Ching-Hung Kao, Yen-Yu Chen
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Publication number: 20210375675Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.Type: ApplicationFiled: October 30, 2020Publication date: December 2, 2021Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Song-Bor Lee, Wen-Hsiung Lu, Po-Hao Tsai, Wen-Che Chang
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Publication number: 20210375748Abstract: A method includes depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant, forming a capacitor over the first passivation layer, and depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line over and electrically connecting to the capacitor, depositing a third passivation layer over the redistribution line, and forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.Type: ApplicationFiled: March 10, 2021Publication date: December 2, 2021Inventors: Chia-Ming HUANG, Ming-Da CHENG, Songbor LEE, Jung-You CHEN, Ching-Hua KUAN, Tzy-Kuang LEE
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Publication number: 20210375672Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.Type: ApplicationFiled: December 4, 2020Publication date: December 2, 2021Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Hao Chun Liu, Po-Hao Tsai, Chih-Hsien Lin, Ching-Wen Hsiao
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Publication number: 20210175071Abstract: A semiconductor device includes a semiconductor substrate, a plurality of isolation structures on the semiconductor substrate, and a plurality of blocking structures disposed directly over the isolation structures. The blocking structures have a lower reflectivity than the isolation structures.Type: ApplicationFiled: February 22, 2021Publication date: June 10, 2021Inventors: Yu-Hsuan Yang, Wen Han Hung, Tzy-Kuang Lee, Chia Ying Lin
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Patent number: 10930502Abstract: A semiconductor device includes a semiconductor substrate, a plurality of isolation structures on the semiconductor substrate, and a plurality of blocking structures disposed directly over the isolation structures. The blocking structures have a lower reflectivity than the isolation structures.Type: GrantFiled: April 15, 2019Date of Patent: February 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Hsuan Yang, Wen Han Hung, Tzy-Kuang Lee, Chia Ying Lin
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Publication number: 20190244807Abstract: A semiconductor device includes a semiconductor substrate, a plurality of isolation structures on the semiconductor substrate, and a plurality of blocking structures disposed directly over the isolation structures. The blocking structures have a lower reflectivity than the isolation structures.Type: ApplicationFiled: April 15, 2019Publication date: August 8, 2019Inventors: Yu-Hsuan Yang, Wen Han Hung, Tzy-Kuang Lee, Chia Ying Lin
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Publication number: 20190164744Abstract: A method for fabricating a semiconductor device includes forming a plurality of isolation structures in a semiconductor substrate and forming a plurality of blocking structures over the isolation structures. The blocking structures have a lower reflectivity than the isolation structures. The method further includes forming a photoresist layer on the semiconductor substrate, exposing the photoresist layer to a light source through a mask, and developing the photoresist layer to create a patterned photoresist feature that covers a first region of a portion of the semiconductor substrate between two of the isolation structures. The portion of the semiconductor substrate having a second region that is exposed.Type: ApplicationFiled: December 13, 2017Publication date: May 30, 2019Inventors: Yu-Hsuan Yang, Wen Han Hung, Tzy-Kuang Lee, Chia Ying Lin
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Patent number: 10283361Abstract: A method for fabricating a semiconductor device includes forming a plurality of isolation structures in a semiconductor substrate and forming a plurality of blocking structures over the isolation structures. The blocking structures have a lower reflectivity than the isolation structures. The method further includes forming a photoresist layer on the semiconductor substrate, exposing the photoresist layer to a light source through a mask, and developing the photoresist layer to create a patterned photoresist feature that covers a first region of a portion of the semiconductor substrate between two of the isolation structures. The portion of the semiconductor substrate having a second region that is exposed.Type: GrantFiled: December 13, 2017Date of Patent: May 7, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Hsuan Yang, Wen Han Hung, Tzy-Kuang Lee, Chia Ying Lin