Abstract: A circuit carrier includes a substrate, a first build-up circuit structure, a second build-up circuit structure, a fine redistribution structure and at least one conductive through hole. The substrate has a top surface and a bottom surface opposite to each other. The first build-up circuit structure is disposed on the top surface of the substrate and electrically connected to the substrate. The second build-up circuit structure is disposed on the bottom surface of the substrate and electrically connected to the substrate. The fine redistribution structure is directly attached on the first build-up circuit structure, wherein a line width and a line spacing of the fine redistribution structure are smaller than those of the first build-up circuit structure. The conductive through hole penetrates the fine redistribution structure and a portion of the first build-up circuit structure and is electrically connected to the fine redistribution structure and the first build-up circuit structure.

Abstract: A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.

Abstract: A circuit board structure has a first flexible circuit board, a second flexible circuit board, and a rigid board structure. The first flexible circuit board has a first dielectric layer and a first conductive circuit. The second flexible circuit board has a second dielectric layer and a second conductive circuit. The rigid board structure connects the first flexible circuit board and the second flexible circuit board. The rigid board structure has a third dielectric layer and a third conductive circuit. A dielectric loss value of the third dielectric layer is less than that of each of the first dielectric layer and the second dielectric layer. The third conductive circuit is electrically connected to the first and second conductive circuits.

Abstract: A vapor chamber structure includes a thermally conductive shell, a capillary structure layer, and a working fluid. The thermally conductive shell includes a first thermally conductive portion and a second thermally conductive portion. The first thermally conductive portion and the second thermally conductive portion are a thermally conductive plate that is integrally formed, and the thermally conductive shell is formed by folding the thermally conductive plate in half and then sealing the thermally conductive plate. The first thermally conductive portion has at least one first cavity, the second thermally conductive portion has at least one second cavity. At least one sealed chamber is defined between the thermally conductive plate, the first cavity and the second cavity. A pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer covers an inner wall of the sealed chamber. The working fluid is filled in the sealed chamber.

Abstract: An inspection apparatus used for inspecting a bare circuit board is provided, where the bare circuit board includes an antenna. The inspection apparatus includes a holding stage, a probing device, and a measurement device. The holding stage can hold the bare circuit board. The measurement device is electrically connected to the probing device and electrically connected to the antenna via the probing device. The measurement device can input a first testing signal to the antenna. The antenna can input a second testing signal to the measurement device after receiving the first testing signal. The measurement device can measure the antenna according to the second testing signal, where the first testing signal and the second testing signal both pass through no active component.

Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.

Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.

Abstract: A circuit board structure includes a dielectric substrate, at least one embedded block, at least one electronic component, at least one first build-up circuit layer, and at least one second build-up circuit layer. The dielectric substrate includes a through cavity penetrating the dielectric substrate. The embedded block is fixed in the through cavity. The embedded block includes a first through hole and a second through hole. The electronic component is disposed in the through hole of the embedded block. The first build-up circuit layer is disposed on the top surface of the dielectric substrate and covers the embedded block. The second build-up circuit layer is disposed on the bottom surface of the dielectric substrate and covers the embedded block.

Abstract: A circuit board structure includes a redistribution structure layer, a build-up circuit structure layer, and a connection structure layer. The redistribution structure layer has a first and second surface, and includes an inner and outer dielectric layer, first connecting pads, and chip pads. A bottom surface of each first connecting pad is aligned with the first surface, and the chip pads are protruded from and located on the second surface. The build-up circuit structure layer includes second connecting pads. The connection structure layer is disposed between the redistribution structure layer and the build-up circuit structure layer and includes a substrate and conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads via the conductive paste pillars, respectively. A top surface of each conductive paste pillar is aligned with the first surface of the redistribution structure layer.

Abstract: A method of manufacturing package structure with following steps is disclosed herein. An insulating composite layer is formed on a metal layer of a carrier board. A chip packaging module including a sealant and a first chip embedded therein is disposed on the insulating composite layer, in which the first chip has a plurality of conductive pads. A first circuit layer module including a dielectric layer and a circuit layer is formed on the chip packaging module, in which the circuit layer is on the dielectric layer and electrically connected to the conductive pads through a conductive vias in the dielectric layer. A second chip is disposed on the first circuit layer module. A second circuit layer module is formed on the first circuit layer module and the second chip. A protecting layer is formed on the second circuit layer module.

Abstract: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.

Abstract: A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.

Abstract: A package carrier includes a first redistribution layer having a first upper surface and a first lower surface and including a plurality of first redistribution circuits, a plurality of conductive through holes, a plurality of photoimageable dielectric layers, and a plurality of chip pads and a second redistribution layer disposed on the first upper surface of the first redistribution layer. The second redistribution layer has a second upper surface and a second lower surface aligned with and directly connected to the first upper surface of the first redistribution layer and includes a plurality of second redistribution circuits, a plurality of conductive structures, a plurality of Ajinomoto build-up Film (ABF) layers, and a plurality of solder ball pads. A line width and a line pitch of each of the first redistribution circuits are smaller than a line width and a line pitch of each of the second redistribution circuits.

Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.

Abstract: An embedded component structure includes a board, an electronic component, and a dielectric material layer. The board has a through cavity. The board includes an insulating core layer and a conductive member. The insulating core layer has a first surface and a second surface opposite thereto. The through cavity penetrates the insulating core layer. The conductive member extends from a portion of the first surface along a portion of the side wall of the through cavity to a portion of the second surface. The electronic component includes an electrode. The electronic component is disposed in the through cavity. The dielectric material layer is at least filled in the through cavity. The connection circuit layer covers and contacts the conductive member and the electrode. A manufacturing method of an embedded component structure is also provided.

Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.

Abstract: A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.

Abstract: A chip package structure includes a substrate, a first chip, a second chip, a bridge, a plurality of first bumps, a plurality of second bumps, a plurality of third bumps and a plurality of solder balls. A first active surface of the first chip and a second active surface of the second chip face a first surface of the substrate. The bridge includes a high-molecular polymer layer and a pad layer located on the high-molecular polymer layer. The first chip is electrically connected to the substrate through the first bumps. The second chip is electrically connected to the substrate through the second bumps. The first chip and the second chip are electrically connected to the pad layer through the third bumps. The first bumps and the second bumps have the same size. The solder balls are disposed on a second surface of the substrate and electrically connected to the substrate.

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

Abstract: A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.