Abstract: A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation.

Abstract: A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation.

Abstract: A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation.

Abstract: A power management chip and a power management device including the power management chip. The power management chip includes at least one power switch and a driver unit for generating a driving signal for driving the at least one power switch, the driver unit including one or more circuit units formed on a same substrate as the at least one power switch.

Abstract: A color optical pen includes a tip unit, a pen body unit attached to the tip unit; a pressure sensor that is disposed in the tip unit and configured to sense at least contact between a display unit of a terminal device and the tip unit; a light source that is disposed in the pen body unit and is configured to output light through the tip unit, if the pressure sensor senses the contact; a color selection switch that is disposed on the pen body, the color selection switch configured to select a color in response to operation by a user; and a driver configured to drive the light source at a frequency or pattern based on operation of the color selection switch.

Abstract: A high side gate driver, a switching chip, and a power device, which respectively include a protection device, are provided. The high side gate driver includes a first terminal configured to receive a first low level driving power supply that is provided to turn off the high side normally-on switch; a first switching device connected to the first terminal; and a protection device connected in series between the first switching device and a gate of the high side normally-on switch, the protection device configured to absorb a majority of a voltage applied to a gate of the high side normally-on switch. The power device includes the high side gate driver. In addition, the switching chip includes a high side normally-on switch, an additional normally-on switch, and a low side normally-on switch, which have a same structure.

Abstract: A logic device includes first and second logic blocks and a connection block. Each of the first and second logic blocks configured to perform at least one function, the first logic blocks connected to first connection lines and the second logic blocks connected to second connection lines. The connection block electrically connected to the first and second logic blocks via the first connection lines and the second connection lines, respectively. The connection block including connection cells configured to select one of multiple connection configurations between the first connection lines and the second connection lines based on a desired function.

Abstract: Image sensors and methods of operating the same. An image sensor includes a pixel array including a plurality of pixels. Each of the plurality of pixels includes a photo sensor, the voltage-current characteristics of which vary according to energy of incident light, and that generates a sense current determined by the energy of the incident light; a reset unit that is activated to generate a reference current, according to a reset signal for resetting at least one of the plurality of pixels; and a conversion unit that converts the sense current and the reference current into a sense voltage and a reference voltage, respectively.

Abstract: A power module including a power device and a periphery circuit configured to suppress a leakage current in the power device. The periphery circuit includes a leakage current detection circuit configured to detect a leakage current from the power device and control operation of the power device based on a result of the detection. The leakage current detection circuit including an input terminal connected to the power device, a plurality of NMOS transistors, a plurality of PMOS transistors connected to the plurality of NMOS transistors, and a comparator.

Abstract: Image sensors and methods of operating the same. An image sensor includes a pixel array including a plurality of pixels. Each of the plurality of pixels includes a photo sensor, the voltage-current characteristics of which vary according to energy of incident light, and that generates a sense current determined by the energy of the incident light; a reset unit that is activated to generate a reference current, according to a reset signal for resetting at least one of the plurality of pixels; and a conversion unit that converts the sense current and the reference current into a sense voltage and a reference voltage, respectively.

Abstract: A storage node of a magnetic memory device includes: a lower magnetic layer, a tunnel barrier layer formed on the lower magnetic layer, and a free magnetic layer formed on the tunnel barrier. The free magnetic layer has a magnetization direction that is switchable in response to a spin current. The free magnetic layer has a cap structure surrounding at least one material layer on which the free magnetic layer is formed.

Abstract: A graphene transistor includes: a gate electrode on a substrate; a gate insulating layer on the gate electrode; a graphene channel on the gate insulating layer; a source electrode and a drain electrode on the graphene channel, the source and drain electrode being separate from each other; and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air gap above the graphene channel between the source electrode and the drain electrode.

Abstract: A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation.

Abstract: A color optical pen includes a tip unit, a pen body unit attached to the tip unit; a pressure sensor that is disposed in the tip unit and configured to sense at least contact between a display unit of a terminal device and the tip unit; a light source that is disposed in the pen body unit and is configured to output light through the tip unit, if the pressure sensor senses the contact; a color selection switch that is disposed on the pen body, the color selection switch configured to select a color in response to operation by a user; and a driver configured to drive the light source at a frequency or pattern based on operation of the color selection switch.

Abstract: A logic device includes first and second logic blocks and a connection block. Each of the first and second logic blocks configured to perform at least one function, the first logic blocks connected to first connection lines and the second logic blocks connected to second connection lines. The connection block electrically connected to the first and second logic blocks via the first connection lines and the second connection lines, respectively. The connection block including connection cells configured to select one of multiple connection configurations between the first connection lines and the second connection lines based on a desired function.

Abstract: A resistive memory device has a structure in which a source, a channel layer, a drain, and a resistive memory layer are sequentially formed in a particular direction, with a gate electrode formed around the channel layer. The source, channel layer, and drain may be vertically stacked on a substrate, and the gate electrode may be formed completely around the channel layer.

Abstract: Nonvolatile memory apparatuses and methods of operating the same. A nonvolatile memory apparatus includes a nonvolatile memory cell array including a plurality of memory cells; an address decoder configured to receive computation data that indicates a computation from among a plurality of computations and an input data for computation, and the address decoder configured to output an address of the nonvolatile memory cell array corresponding to the indicated computation and input data, the nonvolatile memory cell array being configured to output result data stored at the output address, the result data corresponding to a previous computation performed before receipt of the computation data; and a reading unit configured to read the result data output from the nonvolatile memory cell array.

Abstract: A semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a voltage generator configured to generate a test voltage, a graphene transistor configured to receive a gate-source voltage based on the test voltage, and a detector configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor, and output a feedback signal applied to the voltage generator indicating whether the gate-source voltage is the Dirac voltage.

Abstract: A switching element includes: a first electrode; a second electrode; and a silicon-containing chalconitride layer between the first electrode and the second electrode. A switching device includes: a threshold switch material layer between a first electrode and a second electrode. The threshold switch material layer includes a cationic metal element, a chalcogen element, a silicon element and a nitrogen element. A memory device include: a plurality of first wirings arranged in parallel with each other; a plurality of second wirings crossing the first wirings, and arranged in parallel with each other; and a memory cell formed at each intersection of the plurality of first wirings and the plurality of second wirings. The memory cell includes a laminate having a silicon-containing chalconitride layer, an intermediate electrode, and a memory layer.

Abstract: A high side gate driver, a switching chip, and a power device, which respectively include a protection device, are provided. The high side gate driver includes a first terminal configured to receive a first low level driving power supply that is provided to turn off the high side normally-on switch; a first switching device connected to the first terminal; and a protection device connected in series between the first switching device and a gate of the high side normally-on switch, the protection device configured to absorb a majority of a voltage applied to a gate of the high side normally-on switch. The power device includes the high side gate driver. In addition, the switching chip includes a high side normally-on switch, an additional normally-on switch, and a low side normally-on switch, which have a same structure.