Patents by Inventor U N Vasudev

U N Vasudev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11275131
    Abstract: A test and measurement instrument, including at least one port configured to receive a signal from a device under test (DUT), the signal including a current signal acquired across a magnetic core of the DUT and a voltage signal acquired across the magnetic core of the DUT, and one or more processors. The one or more processors are configured to determine a hysteresis loop based on the current signal and the voltage signal, determine a magnetic flux of the magnetic core based on the voltage signal and the current signal for a number of sample points for each cycle, and determine a maximum magnetic flux for all cycles and a hysteresis loop cycle that corresponds to the maximum magnetic flux. A display configured to display at least one of the hysteresis loop, the signal received from the DUT, and the hysteresis loop cycle that corresponds to the maximum magnetic flux.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: March 15, 2022
    Assignee: Tektronix, Inc.
    Inventors: U N Vasudev, Suman Babu Alaparthi, Niranjan R Hegde, Krishna N H Sri
  • Patent number: 10895612
    Abstract: A test and measurement instrument, comprising at least one port configured to receive a signal from a device under test; a user interface configured to receive a user input, the user input indicating magnetic properties of a magnetic material of the device under test, and one or more processors. The one or more processors are configured to generate a hysteresis loop mask based on the magnetic properties of the magnetic material, determine whether the signal received from the device under test violates the hysteresis loop mask, and generate an alert when the signal received from the device under test violates the hysteresis loop mask. The test and measurement instrument may also include a display configured to display the hysteresis loop mask, the signal received from the device under test, and/or the alert.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: January 19, 2021
    Assignee: Tektronix, Inc.
    Inventors: U N Vasudev, Gajendra Kumar Patro, Krishna N H Sri
  • Publication number: 20210013818
    Abstract: A test and measurement device includes an interface configured to acquire analog three-phase signals from a device under test, and a processor programmed to execute instructions that cause the processor to perform a direct-quadrature-zero, DQ0, transformation and produce DQ0 signals based on the analog three-phase signals, and measure performance of the device under test based on the DQ0 signals. A method includes acquiring three-phase signals from a device under test, performing a direct-quadrature-zero, DQ0, transformation on the three-phase signals to produce DQ0 signals, and using the DQ0 signals to measure performance of the device under test.
    Type: Application
    Filed: July 6, 2020
    Publication date: January 14, 2021
    Applicant: Tektronix, Inc.
    Inventors: U N Vasudev, Krishna N H Sri, Vempati L. Bharghavi
  • Publication number: 20200116805
    Abstract: A test and measurement instrument, comprising at least one port configured to receive a signal from a device under test; a user interface configured to receive a user input, the user input indicating magnetic properties of a magnetic material of the device under test, and one or more processors. The one or more processors are configured to generate a hysteresis loop mask based on the magnetic properties of the magnetic material, determine whether the signal received from the device under test violates the hysteresis loop mask, and generate an alert when the signal received from the device under test violates the hysteresis loop mask. The test and measurement instrument may also include a display configured to display the hysteresis loop mask, the signal received from the device under test, and/or the alert.
    Type: Application
    Filed: October 15, 2018
    Publication date: April 16, 2020
    Applicant: Tektronix, Inc.
    Inventors: U N Vasudev, Gajendra Kumar Patro, Krishna N H Sri