Patents by Inventor U-Ting CHEN

U-Ting CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150179612
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 25, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, U-Ting Chen, Shih Pei Chou
  • Publication number: 20150171132
    Abstract: Image sensor devices, methods of manufacture thereof, and semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes bonding a first semiconductor wafer to a second semiconductor wafer, the first semiconductor wafer comprising a substrate and an interconnect structure coupled to the substrate. The method includes removing a portion of the substrate from the first semiconductor wafer to expose a portion of the interconnect structure.
    Type: Application
    Filed: December 18, 2013
    Publication date: June 18, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: U-Ting Chen, Shu-Ting Tsai, Szu-Ying Chen, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 9040891
    Abstract: A method of forming of an image sensor device includes a substrate having a pixel region and a periphery region. A plurality of first trenches is etched in the periphery region. Each of the first trenches has a depth D1. A mask layer is formed over the substrate. The mask layer has a plurality of openings in the pixel region. A spacer is formed in an interior surface of each opening. A plurality of second trenches is etched through each opening having the spacer in the pixel region. Each of the second trenches has a depth D2. The depth D1 is larger than the depth D2.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: May 26, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: U-Ting Chen, Dun-Nian Yaung, Jen-Cheng Liu, Yu-Hao Shih, Chih-Chien Wang, Shih Pei Chou, Wei-Tung Huang, Cheng-Ta Wu
  • Patent number: 9041206
    Abstract: A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Cheng-Jong Wang, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, U-Ting Chen, Jeng-Shyan Lin, Shuang-Ji Tsai
  • Patent number: 8952497
    Abstract: A wafer includes a plurality of chips arranged as rows and columns. A first plurality of scribe lines is between the rows of the plurality of chips. Each of the first plurality of scribe lines includes a metal-feature containing scribe line comprising metal features therein, and a metal-feature free scribe line parallel to, and adjoining, the metal-feature containing scribe line. A second plurality of scribe lines is between the columns of the plurality of chips.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: U-Ting Chen, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Jeng-Shyan Lin, Shuang-Ji Tsai
  • Publication number: 20140264709
    Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.
    Type: Application
    Filed: November 26, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
  • Publication number: 20140077320
    Abstract: A wafer includes a plurality of chips arranged as rows and columns. A first plurality of scribe lines is between the rows of the plurality of chips. Each of the first plurality of scribe lines includes a metal-feature containing scribe line comprising metal features therein, and a metal-feature free scribe line parallel to, and adjoining, the metal-feature containing scribe line. A second plurality of scribe lines is between the columns of the plurality of chips.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: U-Ting Chen, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Jeng-Shyan Lin, Shuang-Ji Tsai
  • Publication number: 20130327921
    Abstract: A method of forming of an image sensor device includes a substrate having a pixel region and a periphery region. A plurality of first trenches is etched in the periphery region. Each of the first trenches has a depth D1. A mask layer is formed over the substrate. The mask layer has a plurality of openings in the pixel region. A spacer is formed in an interior surface of each opening. A plurality of second trenches is etched through each opening having the spacer in the pixel region. Each of the second trenches has a depth D2. The depth D1 is larger than the depth D2.
    Type: Application
    Filed: June 8, 2012
    Publication date: December 12, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: U-Ting CHEN, Dun-Nian YAUNG, Jen-Cheng LIU, Yu-Hao SHIH, Chih-Chien WANG, Shih Pei CHOU, Wei-Tung HUANG, Cheng-Ta WU