Patents by Inventor Uan-Jiun Liu

Uan-Jiun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High-speed serial link clock and data recovery
    Patent number: 7415089
    Abstract: A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The clock generator generates an 8-phase clock signal at half a rate of the transmitted serial data. The phase detector samples input data at four times the standard sampling rate, takes the oversampled data and detects phase transitions therein, i.e., phase lead and lag. The encoder encodes the phase transition data. The confidence counter receives the phase transition data and generates a signal representing the accumulated net effect of the phase transitions. The phase selector receives the confidence counter signal and the 8-phase clock from the clock generator, and determines the optimum phase for data sampling.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: August 19, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Chau-chin Su, Chien-Hsi Lee, Hung-Wen Lu, Hsueh-Chin Lin, Yen-Pin Tseng, Chia-Nan Wang, Uan-Jiun Liu
  • High-speed serial link clock and data recovery
    Publication number: 20050207520
    Abstract: A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The clock generator generates an 8-phase clock signal at half a rate of the transmitted serial data. The phase detector samples input data at four times the standard sampling rate, takes the oversampled data and detects phase transitions therein, i.e., phase lead and lag. The encoder encodes the phase transition data. The confidence counter receives the phase transition data and generates a signal representing the accumulated net effect of the phase transitions. The phase selector receives the confidence counter signal and the 8-phase clock from the clock generator, and determines the optimum phase for data sampling.
    Type: Application
    Filed: March 16, 2004
    Publication date: September 22, 2005
    Inventors: Chau-chin Su, Chien-Hsi Lee, Hung-Wen Lu, Hsueh-Chin Lin, Yen-Pin Tseng, Chia-Nan Wang, Uan-Jiun Liu