Patents by Inventor Uday Chandrasekhar
Uday Chandrasekhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150089324Abstract: A data storage device includes a non-volatile memory and a controller. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit.Type: ApplicationFiled: September 24, 2013Publication date: March 26, 2015Applicant: SANDISK TECHNOLOGIES INC.Inventors: UDAY CHANDRASEKHAR, JIANMIN HUANG, STEVEN SPROUSE, NIAN NILES YANG, XINDE HU
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Publication number: 20150085571Abstract: A data storage device includes a controller that is configured to determine a first read voltage for a first page of a non-volatile memory (e.g., a lower page of a Multi-Level Cell flash memory device). The controller is also configured to determine a second read voltage for a second page (e.g., an upper page) of the non-volatile memory by applying an offset value to the first read voltage. The controller is also configured to store data identifying the first read voltage and the second read voltage.Type: ApplicationFiled: September 24, 2013Publication date: March 26, 2015Applicant: SANDISK TECHNOLOGIES INC.Inventors: Xinde HU, Nian Niles YANG, Uday CHANDRASEKHAR, Jianmin HUANG
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Publication number: 20150063035Abstract: Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a common source line of the data lines being sensed. Data line shielding methods and apparatus disclosed can reduce effects of source line bounce occurring during a sense operation of a memory device.Type: ApplicationFiled: November 7, 2014Publication date: March 5, 2015Applicant: MICRON TECHNOLOGY, INC.Inventor: Uday Chandrasekhar
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Publication number: 20150046770Abstract: Disclosed is a technology to change the parameters by which a read operation is performed in a block with a broken word line. The first method is for reading a broken word line, which may involve changing the voltage on word lines neighboring the broken word line to let the voltage on the broken word line reach the appropriate magnitude through capacitive coupling between word lines. The first method may also involve increasing the time delay before memory cells connected to the broken word line are sensed to allow the voltage on the word line to settle due to increased RC delay. The second method is for reading an unbroken word line in a block with a broken word line, which involves increasing the time delay before memory cells connected to the unbroken word line are sensed while raising the voltages on the word lines neighboring the broken word line.Type: ApplicationFiled: August 9, 2013Publication date: February 12, 2015Applicant: SANDISK TECHNOLOGIES INC.Inventors: Ting Luo, Nian Niles Yang, Chris Avila, Uday Chandrasekhar, Jianmin Huang
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Patent number: 8897071Abstract: Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a common source line of the data lines being sensed. Data line shielding methods and apparatus disclosed can reduce effects of source line bounce occurring during a sense operation of a memory device.Type: GrantFiled: March 12, 2012Date of Patent: November 25, 2014Assignee: Micron Technology, Inc.Inventor: Uday Chandrasekhar
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Patent number: 8885418Abstract: Methods for preventing corruption of lower page data due to a write abort occurring during programming of upper page data by applying an adaptive double pulse programming scheme to non-volatile storage elements are described. In some embodiments, the programming of a first set of non-volatile storage elements to one or more lower-level programming states associated with upper page data (e.g., an A state) may be delayed until a second set of non-volatile storage elements intended to be programmed to one or more upper-level programming states associated with the upper page data (e.g., B or C states) reaches a trigger voltage. Once the trigger voltage has been reached or an appropriate programming delay has passed, then both the first set of non-volatile storage elements and the second set of non-volatile storage elements may be programmed during a common programming phase using double programming pulses.Type: GrantFiled: September 24, 2013Date of Patent: November 11, 2014Assignee: Sandisk Technologies, Inc.Inventors: Sung-Yong Chung, Uday Chandrasekhar, Jianmin Huang, Masaaki Higashitani
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Publication number: 20140321202Abstract: In a flash memory, erase blocks containing shorted or broken word lines may be used, at least in part, to store user data. Such blocks may use different parameters to those used by non-defective blocks, may be subject to different wear leveling, and may store data selected to reduce the number of access operations.Type: ApplicationFiled: April 26, 2013Publication date: October 30, 2014Applicant: SanDisk Technologies, Inc.Inventors: Nian Niles Yang, Uday Chandrasekhar, Yichao Huang, Alexandra Bauche, William S. Wu
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Publication number: 20140286092Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.Type: ApplicationFiled: March 27, 2014Publication date: September 25, 2014Applicant: Micron Technology, Inc.Inventors: Uday Chandrasekhar, Mark A. Helm
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Patent number: 8804419Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.Type: GrantFiled: July 9, 2013Date of Patent: August 12, 2014Assignee: Micron Technology, Inc.Inventors: Uday Chandrasekhar, Mark A. Helm
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Patent number: 8806155Abstract: Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers.Type: GrantFiled: February 25, 2013Date of Patent: August 12, 2014Assignee: Micron Technology, Inc.Inventors: Luyen Vu, Uday Chandrasekhar, Dean Nobunaga
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Publication number: 20140189465Abstract: The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.Type: ApplicationFiled: December 17, 2013Publication date: July 3, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Mark A. Helm, Uday Chandrasekhar
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Patent number: 8711615Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.Type: GrantFiled: July 9, 2013Date of Patent: April 29, 2014Assignee: Micron Technology, Inc.Inventors: Uday Chandrasekhar, Mark A. Helm
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Publication number: 20140068186Abstract: Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers.Type: ApplicationFiled: February 25, 2013Publication date: March 6, 2014Inventors: Luyen Vu, Uday Chandrasekhar, Dean Nobunaga
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Patent number: 8631288Abstract: Methods, devices, and systems for data sensing in a memory system can include performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.Type: GrantFiled: March 14, 2011Date of Patent: January 14, 2014Assignee: Micron Technology, Inc.Inventors: Mark A. Helm, Uday Chandrasekhar
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Publication number: 20130322170Abstract: This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.Type: ApplicationFiled: June 1, 2012Publication date: December 5, 2013Applicant: Micron Technology, Inc.Inventors: Matthew Goldman, Pranav Kalavade, Uday Chandrasekhar, Mark A. Helm
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Publication number: 20130294156Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.Type: ApplicationFiled: July 9, 2013Publication date: November 7, 2013Inventors: Uday Chandrasekhar, Mark A. Helm
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Patent number: 8482975Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.Type: GrantFiled: September 14, 2009Date of Patent: July 9, 2013Assignee: Micron Technology, Inc.Inventors: Uday Chandrasekhar, Mark Helm
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Patent number: 8416628Abstract: Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is transferred to the global sense circuit over local data lines or a global transfer line that is multiplexed to the local data lines. An alternate embodiment uses the local sense circuit to sense both upper and lower groups of memory cells.Type: GrantFiled: September 11, 2012Date of Patent: April 9, 2013Assignee: Micron Technology, Inc.Inventors: Dean Nobunaga, William Kammerer, Uday Chandrasekhar
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Patent number: 8386724Abstract: Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers.Type: GrantFiled: February 19, 2009Date of Patent: February 26, 2013Assignee: Micron Technology, Inc.Inventors: Luyen Vu, Uday Chandrasekhar, Dean Nobunaga
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Publication number: 20130003465Abstract: Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is transferred to the global sense circuit over local data lines or a global transfer line that is multiplexed to the local data lines. An alternate embodiment uses the local sense circuit to sense both upper and lower groups of memory cells.Type: ApplicationFiled: September 11, 2012Publication date: January 3, 2013Inventors: Dean Nobunaga, William Kammerer, Uday Chandrasekhar