Patents by Inventor Uday Kiran Meda

Uday Kiran Meda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11509266
    Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: November 22, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Theertham, Srikanth Manian, Uday Kiran Meda
  • Patent number: 11290118
    Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 29, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Theertham, Jagdish Chand, Yogesh Darwhekar, Subhashish Mukherjee, Jayawardan Janardhanan, Uday Kiran Meda, Arpan Sureshbhai Thakkar, Apoorva Bhatia, Pranav Kumar
  • Publication number: 20220038056
    Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.
    Type: Application
    Filed: October 5, 2021
    Publication date: February 3, 2022
    Inventors: Srinivas THEERTHAM, Srikanth MANIAN, Uday Kiran MEDA
  • Publication number: 20210391866
    Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.
    Type: Application
    Filed: December 21, 2020
    Publication date: December 16, 2021
    Inventors: Srinivas THEERTHAM, Jagdish CHAND, Yogesh DARWHEKAR, Subhashish MUKHERJEE, Jayawardan JANARDHANAN, Uday Kiran MEDA, Arpan Sureshbhai THAKKAR, Apoorva BHATIA, Pranav KUMAR
  • Patent number: 11171601
    Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: November 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Theertham, Srikanth Manian, Uday Kiran Meda