Patents by Inventor Uday M. Hegde

Uday M. Hegde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • State machine generation for multi-buffer electronic systems
    Patent number: 11119921
    Abstract: State machine generation for a multi-buffer electronic system can include receiving, using a processor, a user input specifying a reader policy and a number of a plurality of buffers used by a reader and a writer of the multi-buffer electronic system. A state machine can be generated as a data structure. The state machine has a plurality of states determined based on the number of the plurality of buffers and the reader policy. The state machine allocates different buffers of the plurality of buffers to the reader in temporally accurate order over time. Each state can specify an allocation from the plurality of buffers to the reader and the writer. A state machine description including one or more program code components can be generated, where the one or more program components may be used in an implementation of the reader and an implementation of the writer.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: September 14, 2021
    Assignee: Xilinx, Inc.
    Inventor: Uday M. Hegde
  • System to integrate FPGA functions into a pipeline processing environment
    Publication number: 20030069723
    Abstract: An integrated support tool set that allows a programmer to design an efficient pipelined FPGA.
    Type: Application
    Filed: July 3, 2002
    Publication date: April 10, 2003
    Applicant: DATACUBE, INC.
    Inventor: Uday M. Hegde