Abstract: According to some embodiments, systems an apparatuses may have a communication path to exchange information packets. A processor may process information packets. A buffer pool cache local to the processor may store free buffer handles for information packets when the buffer pool cache local to the processor is not full. A non-local memory may store the free buffer handles for information packets when the buffer pool cache local to the processor is full.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a multi-level queue structure to store data. The multi-level queue structure includes a plurality of queues segregated into more than one priority level. The apparatus further includes a scheduler to schedule transmission of the data from said multi-level queue structure. The scheduler performs multi-level scheduling of the multi-level queue structure utilizing a single data bit vector organized by priority. The single data bit vector indicates occupancy status of associated queues.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a receiver to receive data. A plurality of queues are used to store the data. The apparatus also includes at least one processor to process the data and a transmitter to transmit the data. The apparatus further includes a buffer manager to maintain availability of the buffers and to allocate free buffers. The buffer manager includes a bit vector stored in local memory for maintaining availability status of the plurality of buffers.

Abstract: Managing access to shared memory by a plurality of access entities includes storing a first identifier in a first storage location, the first identifier identifying a data structure in the shared memory; storing a second identifier in a second storage location associated with the first storage location, the second identifier identifying a first access entity; storing the second identifier for access by a second access entity; and signaling the first access entity by the second access entity, before the first access entity accesses the data structure.

Abstract: In general, in one aspect, the disclosure describes a method that includes receiving execution instructions at a processor including multiple programmable processing cores integrated on a single die, selecting subset of at least one of the cores, and loading at least a portion of the execution instructions to the subset of cores while at least one of the other cores continues to process received packets.

Abstract: A system and method to implement cell-based queue management in software. Packets are received from a packet-based medium. In response, packet pointers are enqueued into a virtual output queue (“VOQ”). When a dequeue request to dequeue a cell for the VOQ is received, one of the packet pointers is speculatively prefetched from the VOQ. A cell is then transmitted onto a cell-based fabric containing at least a portion of one of the packets received from the medium and designated by a current packet pointer from among the packet pointers of the VOQ.

Abstract: Method and apparatus to support a large Internet Protocol Forwarding Information Base. A packet is received at a network device, the packet including a destination address. A table is indexed into using a portion of the destination address to locate an entry in the table associated with the portion of the destination address. A pool index is derived from the portion of the destination address and is used to identify a pool of data blocks from among a plurality of pools of data blocks. The entry and the pool of data blocks are navigated to find a next-hop for the packet.

Abstract: A method and apparatus to receive a plurality of packet from an inflow of a single packet flow. In response to receiving the plurality of packets, a plurality of packet pointers is enqueued into multiple physical queues. Each of the plurality of packet pointers designates one of the plurality of packets from the single packet flow. The plurality of packet pointers are dequeued from the multiple physical queues to transmit the plurality of packets along an outflow of the single packet flow.

Abstract: A method and apparatus for meeting a given content throughput using at least one memory channel is generally described. In accordance with one example embodiment of the invention, a method to meet a given content throughput using at least one memory channel comprising, comparing the size of at least a portion of received content to a capacity of a single contiguous location within at least one memory channel to meet a given throughput and determining whether to distribute the at least portion of received content across the at least one memory channel, based at least in part, on the comparison.

Abstract: According to some embodiments, an arrangement of buffers in memory banks is provided.

Abstract: Techniques for optimizing queuing performance include passing, from a ring having M slots, one or more enqueue requests and one or more dequeue requests to a queue manager, and determining whether the ring is full, and if the ring is full, sending only an enqueue request to the queue manager when one of the M slots is next available, otherwise, sending both an enqueue request and a dequeue request to the queue manager.

Abstract: A method and apparatus to provide multicast support on a network device. The network device receives an incoming multicast packet, the multicast packet comprising an incoming multicast header and packet data. The packet data is stored at the network device. A plurality of outgoing multicast headers are generated based on the incoming multicast header. Each outgoing multicast header of the plurality of outgoing multicast headers is attached to the packet data to create a plurality of outgoing multicast packets without making multiple copies of the packet data.

Abstract: According to some embodiments, a packet associated with a blocked port is prevented from being placed in a transmit buffer.

Abstract: A method and apparatus to determine whether a circular queue having N slots is empty or fill. A first queue element is dequeued from a current dequeue slot (“CDS”) of the N slots designated by a CDS pointer. The CDS pointer is incremented to designate a new CDS. It is determined whether the circular queue is empty after the incrementing via executing a check comparing relative positions within the circular queue designated by the CDS pointer and a last enqueue slot (“LES”) pointer. It is determined whether the circular queue is full after setting the LES pointer to designate a new enqueue slot of the circular queue into which a second queue element may be enqueued via re-executing the check.

Abstract: According to some embodiments, a processing element arranges for a packet to be transmitted through a port without storing a packet identifier in a local transmit queue if a number of transmit buffers to be associated with the packet does not exceed a pre-determined threshold.

Abstract: According to some embodiments, an arrangement of buffers in memory banks is provided.

Abstract: According to some embodiments, a symbolic programming system is provided to facilitate the use of buffers stored in a local cache at a network processing element.

Abstract: According to some embodiments, free packet buffers are allocated.

Abstract: A method of executing instructions on a processor includes, receiving a first condition code produced by executing a first instruction during a first clock cycle on an array of engines included in the processor, receiving a second condition code produced by executing a second instruction during a second clock cycle on the array of engines included in the processor, and executing a logical operator on the first and second condition codes during the second clock cycle on the array of engines included in the processor.

Abstract: According to some embodiments, an arrangement of buffers in memory banks is provided.