Patents by Inventor Udayan Ganguly
Udayan Ganguly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11323065Abstract: Accordingly the embodiments herein provide a method for fabricating a neuron oscillator (200a). The neuron oscillator (200a) includes a thermal insulating device connected with a resistor and a capacitor in series to produce self-sustained oscillations, where the resistor and the capacitor are arranged in parallel manner. The neuron oscillator (200a) eliminates a requirement of an additional compensation circuitry for a consistent performance over a time under heating issues. Additionally, an ON/OFF ratio of the neuron oscillator (200a) improves to a broader resistor range. Further, a presence of tunable synaptic memristor functionality of the neuron oscillator (200a) provides a reduced fabrication complexity to a large scale ONN. An input voltage required for the neuron oscillator (200a) is low (2-3 V) which makes it suitable to use with existing circuitries without using any additional converters.Type: GrantFiled: May 28, 2019Date of Patent: May 3, 2022Assignee: INDIAN INSTITUTE OF TECHNOLOGY BOMBAYInventors: Sandip Gangadharrao Lashkare, Vivek Saraswat, Pankaj Subhash Kumbhare, Udayan Ganguly
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Publication number: 20210249300Abstract: Embodiments herein disclose a method providing deposition of Gadolinium Oxide (Gd2O3) on a semiconductor substrate. The method comprises of selecting, in an RF-sputter system, a predefined substrate and depositing, in an Ar-plasma struck, the Gd2O3, over the predefined substrate to obtain a layer of the Gd2O3 over the predefined substrate. The Gd2O3 is grown epitaxially over the predefined substrate. The method further provides performing, annealing, of the layer of the Gd2O3 over the predefined substrate at a predefined temperature for a predefined time and obtaining, a layer of the Gd2O3, over the predefined substrate. Embodiment also provides a method for fabricating Semiconductor on Insulator Substrate (SIS).Type: ApplicationFiled: June 21, 2019Publication date: August 12, 2021Inventors: Udayan Ganguly, Apurba Laha, Suddhasatta Mahapatra, Krista Khiangte
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Publication number: 20210242831Abstract: Accordingly the embodiments herein provide a method for fabricating a neuron oscillator (200a). The neuron oscillator (200a) includes a thermal insulating device connected with a resistor and a capacitor in series to produce self-sustained oscillations, where the resistor and the capacitor are arranged in parallel manner. The neuron oscillator (200a) eliminates a requirement of an additional compensation circuitry for a consistent performance over a time under heating issues. Additionally, an ON/OFF ratio of the neuron oscillator (200a) improves to a broader resistor range. Further, a presence of tunable synaptic memristor functionality of the neuron oscillator (200a) provides a reduced fabrication complexity to a large scale ONN. An input voltage required for the neuron oscillator (200a) is low (2-3 V) which makes it suitable to use with existing circuitries without using any additional converters.Type: ApplicationFiled: May 28, 2019Publication date: August 5, 2021Inventors: Sandip Gangadharrao Lashkare, Vivek Saraswat, Pankaj Subhash Kumbhare, Udayan Ganguly
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Publication number: 20210026604Abstract: Embodiments herein provide a system and a method for generating a random bit string in an Integrated Circuit. Predefined number of One-time Programmable Memory (OTPM) devices are connected in parallel with each OTPM device configured for producing a random bit-string. Current limiting circuit is connected in series with the at least two OTPM devices. Voltage source supplies a predefined voltage to the at least two OTPM devices for producing a breakdown in one of an OTPM device of the at least two OTPM devices resulting in a broken OTPM device while leaving remaining OTPM devices of the at least two OTPM devices unbroken. The random bit string is generated through at least one of the broken OTPM device and a remaining unbroken OTPM device of the at least two OTPM devices.Type: ApplicationFiled: March 20, 2019Publication date: January 28, 2021Inventors: Udayan Ganguly, Sunny Sadana, Sanjay Ashwin Lele
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Patent number: 9530898Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.Type: GrantFiled: October 16, 2014Date of Patent: December 27, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Udayan Ganguly, Yoshitaka Yokota, Jing Tang, Sunderraj Thirupapuliyur, Christopher Sean Olsen, Shiyu Sun, Tze Wing Poon, Wei Liu, Johanes Swenberg, Vicky U. Nguyen, Swaminathar Srinivasan, Jacob Newman
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Patent number: 9502521Abstract: A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.Type: GrantFiled: July 22, 2011Date of Patent: November 22, 2016Assignee: Applied Materials, Inc.Inventors: Udayan Ganguly, Christopher S. Olsen, Sean M. Seutter, Lucien Date
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Patent number: 9023700Abstract: Methods and apparatus for selective one-step nitridation of semiconductor substrates is provided. Nitrogen is selectively incorporated in silicon regions of a semiconductor substrate having silicon regions and silicon oxide regions by use of a selective nitridation process. Nitrogen containing radicals may be directed toward the substrate by forming a nitrogen containing plasma and filtering or removing ions from the plasma, or a thermal nitridation process using selective precursors may be performed. A remote plasma generator may be coupled to a processing chamber, optionally including one or more ion filters, showerheads, and radical distributors, or an in situ plasma may be generated and one or more ion filters or shields disposed in the chamber between the plasma generation zone and the substrate support.Type: GrantFiled: June 9, 2014Date of Patent: May 5, 2015Assignee: Applied Materials, Inc.Inventors: Udayan Ganguly, Theresa Kramer Guarini, Matthew Scott Rogers, Yoshitaka Yokota, Johanes S. Swenberg, Malcolm J. Bevan
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Publication number: 20150102396Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.Type: ApplicationFiled: October 16, 2014Publication date: April 16, 2015Inventors: UDAYAN GANGULY, YOSHITAKA YOKOTA, JING TANG, SUNDERRAJ THIRUPAPULIYUR, CHRISTOPHER SEAN OLSEN, SHIYU SUN, TZE WING POON, WEI LIU, JOHANES SWENBERG, VICKY U. NGUYEN, SWAMINATHAR SRINIVASAN, JACOB NEWMAN
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Publication number: 20140342543Abstract: Methods and apparatus for selective one-step nitridation of semiconductor substrates is provided. Nitrogen is selectively incorporated in silicon regions of a semiconductor substrate having silicon regions and silicon oxide regions by use of a selective nitridation process. Nitrogen containing radicals may be directed toward the substrate by forming a nitrogen containing plasma and filtering or removing ions from the plasma, or a thermal nitridation process using selective precursors may be performed. A remote plasma generator may be coupled to a processing chamber, optionally including one or more ion filters, showerheads, and radical distributors, or an in situ plasma may be generated and one or more ion filters or shields disposed in the chamber between the plasma generation zone and the substrate support.Type: ApplicationFiled: June 9, 2014Publication date: November 20, 2014Inventors: Udayan GANGULY, Theresa Kramer GUARINI, Matthew Scott ROGERS, Yoshitaka YOKOTA, Johanes S. SWENBERG, Malcolm J. BEVAN
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Patent number: 8871645Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.Type: GrantFiled: September 11, 2009Date of Patent: October 28, 2014Assignee: Applied Materials, Inc.Inventors: Udayan Ganguly, Yoshita Yokota, Jing Tang, Sunderraj Thirupapuliyur, Christopher Sean Olsen, Shiyu Sun, Tze Wing Poon, Wei Liu, Johanes Swenberg, Vicky U. Nguyen, Swaminathan Srinivasan, Jacob Newman
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Patent number: 8748259Abstract: Methods and apparatus for selective one-step nitridation of semiconductor substrates is provided. Nitrogen is selectively incorporated in silicon regions of a semiconductor substrate having silicon regions and silicon oxide regions by use of a selective nitridation process. Nitrogen containing radicals may be directed toward the substrate by forming a nitrogen containing plasma and filtering or removing ions from the plasma, or a thermal nitridation process using selective precursors may be performed. A remote plasma generator may be coupled to a processing chamber, optionally including one or more ion filters, showerheads, and radical distributors, or an in situ plasma may be generated and one or more ion filters or shields disposed in the chamber between the plasma generation zone and the substrate support.Type: GrantFiled: February 23, 2011Date of Patent: June 10, 2014Assignee: Applied Materials, Inc.Inventors: Udayan Ganguly, Theresa Kramer Guarini, Matthew Scott Rogers, Yoshitaka Yokota, Johanes S. Swenberg, Malcolm J. Bevan
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Patent number: 8198671Abstract: A flash memory device comprises a substrate comprising silicon with a silicon dioxide layer thereon. A silicon-oxygen-nitrogen layer is on the silicon dioxide layer, and the silicon-oxygen-nitrogen layer comprises a shaped concentration level profile of oxygen through the thickness of the layer. A blocking dielectric layer is on the silicon-oxygen-nitrogen layer, and a gate electrode is on the blocking dielectric layer. Oxygen ions can be implanted into a silicon nitride layer to form the silicon-oxygen-nitrogen layer.Type: GrantFiled: April 22, 2010Date of Patent: June 12, 2012Assignee: Applied Materials, Inc.Inventors: Christopher Sean Olsen, Tze Wing Poon, Udayan Ganguly, Johanes Swenberg
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Patent number: 8163626Abstract: Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process.Type: GrantFiled: June 15, 2010Date of Patent: April 24, 2012Assignee: Applied Materials, Inc.Inventors: Johanes Swenburg, David Chu, Theresa Kramer Guarini, Yonah Cho, Udayan Ganguly, Lucien Date
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Publication number: 20110281429Abstract: A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.Type: ApplicationFiled: July 22, 2011Publication date: November 17, 2011Applicant: Applied Materials, Inc.Inventors: Udayan Ganguly, Christopher S. Olsen, Sean M. Seutter, Lucien Date
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Publication number: 20110217834Abstract: Methods and apparatus for selective one-step nitridation of semiconductor substrates is provided. Nitrogen is selectively incorporated in silicon regions of a semiconductor substrate having silicon regions and silicon oxide regions by use of a selective nitridation process. Nitrogen containing radicals may be directed toward the substrate by forming a nitrogen containing plasma and filtering or removing ions from the plasma, or a thermal nitridation process using selective precursors may be performed. A remote plasma generator may be coupled to a processing chamber, optionally including one or more ion filters, showerheads, and radical distributors, or an in situ plasma may be generated and one or more ion filters or shields disposed in the chamber between the plasma generation zone and the substrate support.Type: ApplicationFiled: February 23, 2011Publication date: September 8, 2011Applicant: APPLIED MATERIALS, INC.Inventors: Udayan Ganguly, Theresa Kramer Guarini, Matthew Scott Rogers, Yoshitaka Yokota, Johanes S. Swenberg, Malcolm J. Bevan
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Patent number: 7972933Abstract: Methods of forming semiconductor devices are provided herein. In some embodiments, a method of forming a semiconductor device may include providing a substrate having an oxide surface and a silicon surface; forming a nitrogen-containing layer on exposed portions of both the oxide and silicon surfaces; and oxidizing the nitrogen-containing layer to selectively remove the nitrogen-containing layer from atop the oxide surface. In some embodiments, an oxide layer is formed atop a remaining portion of the nitrogen-containing layer formed on the silicon feature. In some embodiments, the oxide surface is an exposed surface of a shallow trench isolate region (STI) disposed adjacent to one or more floating gates of a semiconductor device. In some embodiments, the silicon surface is an exposed surface of a silicon or polysilicon floating gate of a semiconductor device.Type: GrantFiled: March 29, 2010Date of Patent: July 5, 2011Assignee: Applied Materials, Inc.Inventors: Christopher S. Olsen, Johanes Swenberg, Udayan Ganguly, Theresa Kramer Guarini, Yonah Cho
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Publication number: 20110101442Abstract: A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.Type: ApplicationFiled: November 2, 2009Publication date: May 5, 2011Applicant: Applied Materials, Inc.Inventors: Udayan Ganguly, Christopher S. Olsen, Sean M. Seutter, Lucien Date
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Publication number: 20110061812Abstract: Apparatus and methods for the manufacture of semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. Disclosed are various single chambers configured to form and/or shape a material layer by oxidizing a surface of a material layer to form an oxide layer; removing at least some of the oxide layer by an etching process; and cyclically repeating the oxidizing and removing processes until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.Type: ApplicationFiled: March 10, 2010Publication date: March 17, 2011Applicant: Applied Materials, Inc.Inventors: Udayan Ganguly, Yoshitaka Yokota, Christopher S. Olsen, Matthew D. Scotney-Castle, Vicky Nguyen, Swaminathan Srinivasan, Wei Liu, Johanes F. Swenberg, Jose A. Marin, Aijit Balakrishna, Jacob Newman, Stephen C. Hickerson
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Publication number: 20110065276Abstract: Apparatus and methods for the manufacture of semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. Disclosed are various single chambers configured to form and/or shape a material layer by oxidizing a surface of a material layer to form an oxide layer; removing at least some of the oxide layer by an etching process; and cyclically repeating the oxidizing and removing processes until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.Type: ApplicationFiled: March 10, 2010Publication date: March 17, 2011Applicant: Applied Materials, Inc.Inventors: Udayan Ganguly, Joseph M. Ranish, Aaron M. Hunter, Jing Tang, Christopher S. Olsen, Matthew D. Scotney-Castle, Vicky Nguyen, Swaminathan Srinivasan, Wei Liu, Johanes F. Swenberg, Shiyu Sun
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Publication number: 20110061810Abstract: Apparatus and methods for the manufacture of semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. Disclosed are various single chambers configured to form and/or shape a material layer by oxidizing a surface of a material layer to form an oxide layer; removing at least some of the oxide layer by an etching process; and cyclically repeating the oxidizing and removing processes until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.Type: ApplicationFiled: March 10, 2010Publication date: March 17, 2011Applicant: Applied Materials, Inc.Inventors: Udayan Ganguly, Joseph M. Ranish, Aaron M. Hunter, Jing Tang, Christopher S. Olsen, Matthew D. Scotney-Castle, Vicky Nguyen, Swaminathan Srinivasan, Johanes F. Swenberg, Anchuan Wang, Nitin K. Ingle, Manish Hemkar, Jose A. Marin