Abstract: A FPGA and DAC based shaped clock controller for EMCCD devices is provided. The controller may allow clocking of an EMCCD in low noise mode to enable imaging single photon events at each pixel in the image. An algorithm for spatially selective gain clocking may enable an EMCCD camera to image very dim objects near very bright objects in a high contrast instrument. Spatially selective gain clocking is one of the first steps that is required to begin to unravel objects near a bright source.

Abstract: A digital radar system includes a transmitter, the transmitter configured to transmit a signal; a receiver, the receiver configured to receive a return signal; and two analog to digital conversion (ADC) units, the ADC units configured to digitize the return signal at a rate higher than a Nyquist rate for the transmitted signal. A method of operating a digital radar includes transmitting a signal via a transmitter; receiving a return signal via a receiver; and digitizing the return signal by two analog to digital conversion (ADC) units at a rate higher than a Nyquist rate for the transmitted signal.