Patents by Inventor Udayan Mukherjee

Udayan Mukherjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7958380
    Abstract: In one embodiment, the present invention includes a method determining if an access queue associated with a channel of a memory has been empty for a predetermined time period and if so, de-asserting a clock enable signal for all ranks of the channel of the memory, otherwise providing a next memory access request from the access queue to the channel of the memory. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: June 7, 2011
    Assignee: Intel Corporation
    Inventors: Sandeep K. Jain, Howard David, Udayan Mukherjee
  • Patent number: 7817394
    Abstract: A method according to one embodiment may include discovering, by software, at least one variable from at least one component populated on a shelf system. The method may also include performing, by the software, at least one shelf management function based on at least one variable. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: October 19, 2010
    Assignee: Intel Corporation
    Inventors: Udayan Mukherjee, Chetan Hiremath
  • Publication number: 20100257294
    Abstract: In some embodiments a system includes one or more processing nodes, a backplane, and one or more links to couple the one or more processing nodes to the backplane, wherein at least one of the one or more links is configurable as a standard Input/Output link and/or as a proprietary link. Other embodiments are described and claimed.
    Type: Application
    Filed: April 6, 2009
    Publication date: October 7, 2010
    Inventors: Greg Regnier, Sorin Iacobovici, Chetan Hiremath, Udayan Mukherjee, Nilesh Jain
  • Patent number: 7774651
    Abstract: A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults in the system is also disclosed.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: August 10, 2010
    Assignee: Intel Corporation
    Inventors: Udayan Mukherjee, Aniruddha Kundu
  • Publication number: 20100191997
    Abstract: A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model.
    Type: Application
    Filed: April 1, 2010
    Publication date: July 29, 2010
    Applicant: INTEL CORPORATION
    Inventors: Rakesh Dodeja, Neelam Chandwani, Chetan Hiremath, Udayan Mukherjee, Anthony Ambrose
  • Patent number: 7752468
    Abstract: A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: July 6, 2010
    Assignee: Intel Corporation
    Inventors: Rakesh Dodeja, Neelam Chandwani, Chetan Hiremath, Udayan Mukherjee, Anthony Ambrose
  • Patent number: 7702966
    Abstract: A method for managing a system includes monitoring a plurality of applications running in the system for errors. A prediction is made as to whether errors detected would result in a failure. Fault recovery is initiated in response to a failure prediction. According to one aspect of the present invention, monitoring the plurality of applications includes reading error recorders associated with error occurrence. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Neelam Chandwani, Udayan Mukherjee, Chetan Hiremath, Rakesh Dodeja
  • Patent number: 7558849
    Abstract: A hardware management module is enabled to perform hardware management for a modular platform system that includes a plurality of modular platform shelves coupled via one or more communication links in a network. Hardware management to include monitoring board interfaces resident on one or more backplanes within the plurality of modular platform shelves, detecting when a board is received and coupled to a board interface and performing one or more hardware management functions to include obtaining field replaceable unit information from the detected board.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: July 7, 2009
    Assignee: Intel Corporation
    Inventors: Neelam Chandwani, Udayan Mukherjee, Chetan Hiremath, Rakesh Dodeja
  • Publication number: 20080294928
    Abstract: In one embodiment, the present invention includes a method determining if an access queue associated with a channel of a memory has been empty for a predetermined time period and if so, de-asserting a clock enable signal for all ranks of the channel of the memory, otherwise providing a next memory access request from the access queue to the channel of the memory. Other embodiments are described and claimed.
    Type: Application
    Filed: May 22, 2007
    Publication date: November 27, 2008
    Inventors: Sandeep K. Jain, Howard David, Udayan Mukherjee
  • Patent number: 7424396
    Abstract: Faults are monitored with information from agents for a plurality of sensors located on a plurality of circuit boards. A policy containing a error event thresholds against which the stored sensor information can be compared. Actions can be initiated by a fault module when one or more of the error event thresholds is exceeded.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Rakesh Dodeja, Neelam Chandwani, Chetan Hiremath, Wen Wei, Udayan Mukherjee
  • Patent number: 7409594
    Abstract: A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults in the system is also disclosed.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: August 5, 2008
    Assignee: Intel Corporation
    Inventors: Udayan Mukherjee, Aniruddha Kundu
  • Publication number: 20080104453
    Abstract: A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults in the system is also disclosed.
    Type: Application
    Filed: January 7, 2008
    Publication date: May 1, 2008
    Inventors: Udayan Mukherjee, Aniruddha Kundu
  • Publication number: 20070283178
    Abstract: A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 6, 2007
    Inventors: Rakesh Dodeja, Neelam Chandwani, Chetan Hiremath, Udayan Mukherjee, Anthony Ambrose
  • Patent number: 7283921
    Abstract: A modeling module is disclosed that couples to a modular platform chassis. The modeling module includes a resident management controller to implement a test to model a component layout for a module to be received and coupled to the modular platform chassis. The test includes an operating thermal load for a component resident on the module at a given location. The module has a dimensional length and width that is similar to that of the modeling module. The modeling module also includes a thermal load device that is responsive to the management controller. The thermal load device is to implement at least a portion of the test by simulating the operating thermal load for the component resident on the module at the given location.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: October 16, 2007
    Assignee: Intel Corporation
    Inventors: Neelam Chandwani, Udayan Mukherjee, Wen Wei, Chetan Hiremath, Rakesh Dodeja, Kevin W. Bross
  • Publication number: 20070089011
    Abstract: Faults are monitored with information from agents for a plurality of sensors located on a plurality of circuit boards. A policy containing a error event thresholds against which the stored sensor information can be compared. Actions can be initiated by a fault module when one or more of the error event thresholds is exceeded.
    Type: Application
    Filed: September 26, 2005
    Publication date: April 19, 2007
    Inventors: Rakesh Dodeja, Neelam Chandwani, Chetan Hiremath, Wen Wei, Udayan Mukherjee
  • Publication number: 20070055914
    Abstract: A method for managing a system includes monitoring a plurality of applications running in the system for errors. A prediction is made as to whether errors detected would result in a failure. Fault recovery is initiated in response to a failure prediction. According to one aspect of the present invention, monitoring the plurality of applications includes reading error recorders associated with error occurrence. Other embodiments are described and claimed.
    Type: Application
    Filed: September 7, 2005
    Publication date: March 8, 2007
    Inventors: Neelam Chandwani, Udayan Mukherjee, Chetan Hiremath, Rakesh Dodeja
  • Publication number: 20070038732
    Abstract: A hardware management module is enabled to perform hardware management for a modular platform system that includes a plurality of modular platform shelves coupled via one or more communication links in a network. Hardware management to include monitoring board interfaces resident on one or more backplanes within the plurality of modular platform shelves, detecting when a board is received and coupled to a board interface and performing one or more hardware management functions to include obtaining field replaceable unit information from the detected board.
    Type: Application
    Filed: August 10, 2005
    Publication date: February 15, 2007
    Inventors: Neelam Chandwani, Udayan Mukherjee, Chetan Hiremath, Rakesh Dodeja
  • Publication number: 20070038407
    Abstract: A modeling module is disclosed that couples to a modular platform chassis. The modeling module includes a resident management controller to implement a test to model a component layout for a module to be received and coupled to the modular platform chassis. The test includes an operating thermal load for a component resident on the module at a given location. The module has a dimensional length and width that is similar to that of the modeling module. The modeling module also includes a thermal load device that is responsive to the management controller. The thermal load device is to implement at least a portion of the test by simulating the operating thermal load for the component resident on the module at the given location.
    Type: Application
    Filed: August 10, 2005
    Publication date: February 15, 2007
    Inventors: Neelam Chandwani, Udayan Mukherjee, Wen Wei, Chetan Hiremath, Rakesh Dodeja, Kevin Bross
  • Publication number: 20060023384
    Abstract: A method according to one embodiment may include discovering, by software, at least one variable from at least one component populated on a shelf system. The method may also include performing, by the software, at least one shelf management function based on at least one variable. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Application
    Filed: July 28, 2004
    Publication date: February 2, 2006
    Inventors: Udayan Mukherjee, Chetan Hiremath
  • Publication number: 20060010352
    Abstract: A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults in the system is also disclosed.
    Type: Application
    Filed: July 6, 2004
    Publication date: January 12, 2006
    Inventors: Udayan Mukherjee, Aniruddha Kundu