Patents by Inventor Uddalak Bhattacharya
Uddalak Bhattacharya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11735521Abstract: Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.Type: GrantFiled: October 25, 2021Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Yu-Lin Chao, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya
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Patent number: 11348651Abstract: Memory cell circuitry is disclosed. The memory cell circuitry includes a first transistor configured to have a threshold voltage of the first transistor modulated by hot carrier injection, a second transistor coupled to the first transistor and configured to have a threshold voltage of the second transistor modulated by hot carrier injection, a word line coupled to a gate of the first transistor and to a gate of the second transistor, a first bit line coupled to the first transistor and a second bit line coupled to the second transistor. In addition, the memory cell circuitry includes a source line coupled to the drain of the first transistor and to the drain of the second transistor, the word line and the source line configured to cause hot carrier injection (HCI) into the first transistor when a first supply voltage is applied to the word line and the source line, and the second bit line is floated and the first bit line is grounded.Type: GrantFiled: September 28, 2018Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Sarvesh Kulkarni, Vincent Dorgan, Inanc Meric, Venkata Krishna Rao Vangara, Uddalak Bhattacharya, Jeffrey Hicks
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Publication number: 20220045001Abstract: Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.Type: ApplicationFiled: October 25, 2021Publication date: February 10, 2022Inventors: Yu-Lin CHAO, Sarvesh H. KULKARNI, Vincent E. DORGAN, Uddalak BHATTACHARYA
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Patent number: 11239149Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.Type: GrantFiled: April 2, 2018Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Vincent Dorgan, Jeffrey Hicks, Uddalak Bhattacharya, Zhanping Chen, Walid Hafez
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Patent number: 11189564Abstract: Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.Type: GrantFiled: April 2, 2018Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Yu-Lin Chao, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya
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Publication number: 20200105356Abstract: Memory cell circuitry is disclosed. The memory cell circuitry includes a first transistor configured to have a threshold voltage of the first transistor modulated by hot carrier injection, a second transistor coupled to the first transistor and configured to have a threshold voltage of the second transistor modulated by hot carrier injection, a word line coupled to a gate of the first transistor and to a gate of the second transistor, a first bit line coupled to the first transistor and a second bit line coupled to the second transistor. In addition, the memory cell circuitry includes a source line coupled to the drain of the first transistor and to the drain of the second transistor, the word line and the source line configured to cause hot carrier injection (HCI) into the first transistor when a first supply voltage is applied to the word line and the source line, and the second bit line is floated and the first bit line is grounded.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Sarvesh KULKARNI, Vincent DORGAN, Inanc MERIC, Venkata Krishna Rao VANGARA, Uddalak BHATTACHARYA, Jeffrey HICKS
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Publication number: 20190304907Abstract: Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.Type: ApplicationFiled: April 2, 2018Publication date: October 3, 2019Inventors: Yu-Lin CHAO, Sarvesh H. KULKARNI, Vincent E. DORGAN, Uddalak BHATTACHARYA
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Publication number: 20190304893Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.Type: ApplicationFiled: April 2, 2018Publication date: October 3, 2019Inventors: Vincent DORGAN, Jeffrey HICKS, Uddalak BHATTACHARYA, Zhanping CHEN, Walid M. HAFEZ
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Patent number: 10249597Abstract: Systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems are described. A stacked semiconductor package includes a processor functional silicon die at a first layer of the stacked semiconductor package; one or more memory dies forming a corresponding one or more memory layers of the stacked semiconductor package; a plurality of Through Silicon Vias (TSV s) formed through the one or more memory dies; a plurality of physical memory interfaces electrically interfacing the one or more memory dies to the processor functional silicon die at the first layer through the memory layers via the plurality of TSVs; and a redundant physical memory interface formed by a redundant TSV traversing through the memory layers to the processor functional silicon die at the first layer through which to reroute a memory signal path from a defective physical memory interface at a defective TSV to a functional signal path traversing the redundant TSV.Type: GrantFiled: September 30, 2016Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Kalyan C. Kolluru, Pete D. Vogt, Christopher J. Nelson, Amande B. Trang, Uddalak Bhattacharya
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Publication number: 20180096971Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: LAKSHMINARAYANA PAPPU, KALYAN C. KOLLURU, PETE D. VOGT, CHRISTOPHER J. NELSON, AMANDE B. TRANG, UDDALAK BHATTACHARYA
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Patent number: 9679845Abstract: Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse programming voltage may open necked fuse segments to affect operation of an IC. In embodiments, the fuse structure includes a pair of neighboring interconnect lines equidistant from a center interconnect line. In further embodiments, the center interconnect line, and at least one of the neighboring interconnect lines, include line segments of lateral widths that differ by a same, and complementary amount. In further embodiments, the center interconnect line is interconnected at opposite ends of a necked line segment. In further embodiments, the necked line segment is fabricated with pitch-reducing spacer-based patterning process.Type: GrantFiled: May 8, 2014Date of Patent: June 13, 2017Assignee: Intel CorporationInventors: Zhanping Chen, Andrew W. Yeoh, Seongtae Jeong, Uddalak Bhattacharya, Charles H. Wallace
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Patent number: 9607687Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.Type: GrantFiled: November 20, 2015Date of Patent: March 28, 2017Assignee: Intel CorporationInventors: Pramod Kolar, Gunjan H. Pandya, Uddalak Bhattacharya, Zheng Guo
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Publication number: 20170018499Abstract: Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse programming voltage may open necked fuse segments to affect operation of an IC. In embodiments, the fuse structure includes a pair of neighboring interconnect lines equidistant from a center interconnect line. In further embodiments, the center interconnect line, and at least one of the neighboring interconnect lines, include line segments of lateral widths that differ by a same, and complementary amount. In further embodiments, the center interconnect line is interconnected at opposite ends of a necked line segment. In further embodiments, the necked line segment is fabricated with pitch-reducing spacer-based patterning process.Type: ApplicationFiled: May 8, 2014Publication date: January 19, 2017Inventors: Zhanping Chen, Andrew W. Yeoh, Seongtae Jeong, Uddalak Bhattacharya, Charles H. Wallace
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Publication number: 20160078926Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.Type: ApplicationFiled: November 20, 2015Publication date: March 17, 2016Applicant: Intel CorporationInventors: Pramod Kolar, Gunjan H. Pandya, Uddalak Bhattacharya, Zheng Guo
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Patent number: 9208853Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.Type: GrantFiled: March 15, 2013Date of Patent: December 8, 2015Assignee: Intel CorporationInventors: Pramod Kolar, Gunjan H. Pandya, Uddalak Bhattacharya, Zheng Guo
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Publication number: 20140269019Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Pramod Kolar, Gunjan H. Pandya, Uddalak Bhattacharya, Zheng Guo
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Patent number: 8451670Abstract: Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.Type: GrantFiled: September 23, 2010Date of Patent: May 28, 2013Assignee: Intel CorporationInventors: Pramod Kolar, Fatih Hamzaoglu, Yih Wang, Eric A Karl, Yong-Gee Ng, Uddalak Bhattacharya, Kevin X. Zhang, Hyunwoo Nho
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Publication number: 20120075938Abstract: Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.Type: ApplicationFiled: September 23, 2010Publication date: March 29, 2012Inventors: Pramod Kolar, Fatih Hamzaoglu, Yih Wang, Eric A. Karl, Yong-Gee NG, Uddalak Bhattacharya, Kevin X. Zhang, Hyunwoo Nho
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Patent number: 6956918Abstract: A method for bi-directional data synchronization between different clock frequencies is described wherein a state machine counter is provided a first clock signal having a first frequency. The state machine counter is then provided a second clock signal having a second frequency that is an integer multiple of the first clock frequency. The state machine counter has an integer number of states equivalent to the ratio of the second clock signal frequency to the first clock signal frequency. The first clock signal is applied to reset the state machine counter to an initial state. The state machine counter generates an intermediate clock signal whenever the state machine increments through all states to return to the initial state. The intermediate clock is then applied to synchronize data between the first clock frequency and the second clock frequency.Type: GrantFiled: June 27, 2001Date of Patent: October 18, 2005Assignee: Intel CorporationInventors: Wenliang Chen, Uddalak Bhattacharya
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Publication number: 20030002606Abstract: A method for bi-directional data synchronization between different clock frequencies is described wherein a state machine counter is provided a first clock signal having a first frequency. The state machine counter is then provided a second clock signal having a second frequency that is an integer multiple of the first clock frequency. The state machine counter has an integer number of states equivalent to the ratio of the second clock signal frequency to the first clock signal frequency. The first clock signal is applied to reset the state machine counter to an initial state. The state machine counter generates an intermediate clock signal whenever the state machine increments through all states to return to the initial state. The intermediate clock is then applied to synchronize data between the first clock frequency and the second clock frequency.Type: ApplicationFiled: June 27, 2001Publication date: January 2, 2003Inventors: Wenliang Chen, Uddalak Bhattacharya