Patents by Inventor Udey Chaudhry

Udey Chaudhry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5841660
    Abstract: A method for process control which uses discrete lots in which each lot is uniquely identified. The process is modeled with a precedence rule which allows concurrent processing of each discrete lot. Lots are processed simultaneously within different processing steps in such a way as to maintain the unity of the lot while tracking the lot at all times during processing.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: November 24, 1998
    Assignee: Motorola, Inc.
    Inventors: Jeffrey A. Robinson, Udey Chaudhry, Timothy L. Olson
  • Patent number: 5764520
    Abstract: A method for controlling production lots which deals with production lots comprising a plurality of discrete units distributed among a plurality of locations. A first event is triggered when a first unit from a first production lot enters a processing step. A second event is triggered when a last unit from the first production lot leaves the processing step.
    Type: Grant
    Filed: July 5, 1995
    Date of Patent: June 9, 1998
    Assignee: Motorola, Inc.
    Inventors: Jeffrey A. Robinson, Udey Chaudhry
  • Patent number: 5473192
    Abstract: A semiconductor chip module is formed by providing at least one semiconductor chip and a semiconductor substrate and bonding the semiconductor chip to the semiconductor substrate without the use of an epoxy or a metallic layer to create a bond between the semiconductor chip and the semiconductor substrate. The semiconductor chip of the semiconductor chip module is electrically connected to an external, electrical interconnection system. The semiconductor substrate has similar thermal properties to the semiconductor chip, this thermal mismatch present between a semiconductor chip and a metallic heatsink in conventional external, electrical interconnection systems is eliminated.
    Type: Grant
    Filed: May 4, 1993
    Date of Patent: December 5, 1995
    Assignee: Motorola, Inc.
    Inventors: Theodore R. Golubic, Udey Chaudhry
  • Patent number: 5278446
    Abstract: A plastic package (10) with a heat sink (11, 27, 28, 32) has a stress relief wall (18, 21, 33) formed on its upper surface. A semiconductor die (12) is mounted on the heat sink (11, 27, 28, 32) such that the top of a semiconductor die (12) is below the level of the top of the wall (18, 21, 33), and the wall (18, 21, 33) absorbs stresses which otherwise would be applied to the semiconductor die (12). The package (10) is simple to fabricate and assemble, and provides a mold lock (23, 24, 31) which serves to hold the plastic material (13) tightly to the heat sink (11, 27, 28, 32). Extra die bond material (26) can be used to increase heat flow without compromising other characteristics of the package (10).
    Type: Grant
    Filed: July 6, 1992
    Date of Patent: January 11, 1994
    Assignee: Motorola, Inc.
    Inventors: Benamanahalli K. Nagaraj, Timothy L. Olson, Udey Chaudhry
  • Patent number: 5105258
    Abstract: A layer of aluminum is formed on a surface of a thermal expansion buffer which is used in a semiconductor package. A semiconductor die is attached to the aluminum using a die attach material. An electrical connection for the die is created by attaching a wire from the semiconductor die to the aluminum surface of the buffer. This provides a reliable semiconductor package useful in a high temperature environment.
    Type: Grant
    Filed: November 21, 1990
    Date of Patent: April 14, 1992
    Assignee: Motorola, Inc.
    Inventors: Duane C. Silvis, Udey Chaudhry, James R. Eckert, Edward J. Mischen