Abstract: In a Plug and Play environment different kinds of EEPROMs can be used having different access protocols without having to add an additional pin to the EEPROM to indicate its type. The first type of EEPROM has a code which indicates the first type stored on a predetermined address whereas the second type of EEPROM having a different read protocol has another code which indicates the second type stored on a consecutive address. When the Plug and Play controller accesses the EEPROM for a read either the code 1 or code 2 is outputted whereby the appropriate read protocol is identified.

Abstract: In a clock generator (100), an oscillator (30) supplies an oscillator signal (38) to a first trigger (10) and to a second trigger (20). The triggers change the oscillator signal (38) to a first and a second trigger signal (18, 28). The second trigger (20) has a larger hysteresis range than the first trigger (10), so that the first trigger signal (18) starts toggling before the second trigger signal (28) starts toggling. A detector (40) determines that the second trigger signal (28) toggles at least three times, that means that the oscillator signal (38) goes over the larger hysteresis range in two directions. The detector (40) provides a result to a control circuit (50) which derives a clock signal (98) from the first trigger signal (18).

Abstract: A circuit (100) comprises a built-in test circuit (150) which verifies the proper operation of input cells (130) when they receive signals at a first level (71) and at a second level (72). The test circuit (160) comprises a first and a second logic (110, 120) which receive power only when a test is performed. Thereby power consumption of the test circuit (160) is reduced. The first and the second logic (110, 120) are conveniently formed by a combination of parallel coupled transistors acting in an logical OR-function.

Abstract: Output on Multiple Time Division Multiplexer (TDM) HDLC lines (28) is selectively and gracefully throttled. A throttling signal (99) is asserted whenever either the output FIFO queue (58) is almost full or the input FIFO queue (56) is almost empty. Whenever an in frame/out of frame state transition occurs for a given logical channel, a check is made whether throttling is required (292, 296). If throttling is required, an HDLC flag byte is transmitted (291, 299), delaying all such state transitions until the throttling signal (99) is no longer asserted.