Abstract: Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package.

Abstract: Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package.

Abstract: A method for managing clock frequency in a multi-core integrated circuit includes determining a minimum allowable operating clock frequency and a maximum allowable operating clock frequency for an integrated circuit having a plurality of processor cores. A plurality of clock sources is configured to provide a corresponding plurality of clock frequencies between the minimum allowable operating clock frequency and the maximum allowable operating clock frequency. A total number of active processor cores is determined. If it is determined that all of the plurality the processor cores are active, all active processor cores are operated at the minimum allowable operating clock frequency. If it is determined that the total number of active processor cores is lower than a threshold number, the clock frequency of one or more active processor cores is increased based on available electrical current budget.

Abstract: A method for managing clock frequency in a multi-core integrated circuit includes determining a minimum allowable operating clock frequency and a maximum allowable operating clock frequency for an integrated circuit having a plurality of processor cores. A plurality of clock sources is configured to provide a corresponding plurality of clock frequencies between the minimum allowable operating clock frequency and the maximum allowable operating clock frequency. A total number of active processor cores is determined. If it is determined that all of the plurality the processor cores are active, all active processor cores are operated at the minimum allowable operating clock frequency. If it is determined that the total number of active processor cores is lower than a threshold number, the clock frequency of one or more active processor cores is increased based on available electrical current budget.

Abstract: Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package.

Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.