Patents by Inventor Udin Salim

Udin Salim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic latch circuitry
    Patent number: 6087872
    Abstract: A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: July 11, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hamid Partovi, Robert C. Burd, Udin Salim, Frederick Weber, Luigi Di Gregorio, Donald A. Draper
  • Latching method
    Patent number: 5990717
    Abstract: A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: November 23, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hamid Partovi, Robert C. Burd, Udin Salim, Frederick Weber, Luigi Di Gregorio, Donald A. Draper
  • Latching methodology
    Patent number: 5774005
    Abstract: A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially setup and clock-to-output times. The flip-flop consumes no static power.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: June 30, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hamid Partovi, Robert C. Burd, Udin Salim, Frederick Weber, Luigi DiGregorio, Donald A. Draper
  • Dynamic latching device
    Patent number: 5764089
    Abstract: A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: June 9, 1998
    Assignee: Altera Corporation
    Inventors: Hamid Partovi, Robert C. Burd, Udin Salim, Frederick Weber, Luigi Di Gregorio, Donald A. Draper