Abstract: According to various embodiments, an electronic circuit includes a plurality of clock generators wherein each clock generator is configured to store a counter value, to receive a reference clock, to change the counter value in accordance with the reference clock and to generate at least one clock signal based on the counter value. The circuit also includes a comparator configured to receive, for each of at least two of the plurality of clock generators, the counter value and compare the received counter values and an error handling circuit configured to initiate an error handling based on the result of the comparison.

Abstract: According to various embodiments, an electronic circuit includes a plurality of clock generators wherein each clock generator is configured to store a counter value, to receive a reference clock, to change the counter value in accordance with the reference clock and to generate at least one clock signal based on the counter value. The circuit also includes a comparator configured to receive, for each of at least two of the plurality of clock generators, the counter value and compare the received counter values and an error handling circuit configured to initiate an error handling based on the result of the comparison.

Abstract: A functional clock generator, including: an oscillator configured to generate an oscillator clock having an oscillator clock frequency; a control value generator configured to generate control values to ramp the oscillator clock frequency between a first frequency and a second, higher frequency; a Phase-Locked Loop (PLL) configured to generate a PLL clock having the second frequency; and a selector configured to switch between selecting the oscillator clock and the PLL clock as a functional clock when the oscillator clock frequency and the PLL clock frequency are substantially equal.

Abstract: A method and a computer program for configuring an integrated circuit design for static timing analysis include receiving module data representative of a hierarchy of modules in an integrated circuit design. A configuration item is selected from a list of configuration items for at least one of the modules. The module data is configured for the module from the selected configuration item into a static timing analysis scenario for performing a static timing analysis of the configured module data.

Abstract: A method and a computer program for configuring an integrated circuit design for static timing analysis include receiving module data representative of a hierarchy of modules in an integrated circuit design. A configuration item is selected from a list of configuration items for at least one of the modules. The module data is configured for the module from the selected configuration item into a static timing analysis scenario for performing a static timing analysis of the configured module data.