Patents by Inventor Udo Götschkes

Udo Götschkes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10468248
    Abstract: In various embodiments, a method is provided. The method may include forming a buried electrically charged region at a predefined position in a first layer in such a way that the buried electrically charged region generates an electric field having a lateral inhomogeneous field distribution above the first layer, and forming a second layer above the first layer using the field distribution in such a way that a structure of the second layer correlates with the position of the buried electrically charged region.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: November 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Heiko Aßmann, Felix Braun, Marcus Dankelmann, Stefan Doering, Karsten Friedrich, Udo Goetschkes, Andreas Greiner, Ralf Rudolf, Jens Schneider
  • Publication number: 20170294299
    Abstract: In various embodiments, a method is provided. The method may include forming a buried electrically charged region at a predefined position in a first layer in such a way that the buried electrically charged region generates an electric field having a lateral inhomogeneous field distribution above the first layer, and forming a second layer above the first layer using the field distribution in such a way that a structure of the second layer correlates with the position of the buried electrically charged region.
    Type: Application
    Filed: April 12, 2017
    Publication date: October 12, 2017
    Inventors: Heiko Assmann, Felix Braun, Marcus Dankelmann, Stefan Doering, Karsten Friedrich, Udo Goetschkes, Andreas Greiner, Ralf Rudolf, Jens Schneider
  • Patent number: 6982495
    Abstract: A mark configuration for the alignment and/or determination of a relative position of at least two planes in relation to one another in a substrate and/or in layers on a substrate during lithographic exposure, in particular, in the case of a wafer during the production of DRAMs, includes a mark structure, and at least one layer of a definable thickness underneath the mark structure for adjusting the physical position of the mark structure relative to a reference plane in or on the substrate. Also provided is a wafer having such a configuration and a process for providing such a configuration. The invention allows a mark configuration to have mark structures exhibiting good contrast regardless of the design or the process conditions.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: January 3, 2006
    Assignee: Infineon Technologies AG
    Inventors: Hans-Georg Fröhlich, Johannes Kowalewski, Udo Götschkes, Frank Hübinger, Gerd Krause, Heike Langnickel, Antje Lässig, Reiner Trinowitz