Abstract: A modular underground utilities vault enclosure and distribution system providing an integrated utilities interconnection system within a single modular enclosure and a single unified set of utility service connections leading from the vault to the premises of one or several utilities customers. The vault design comprises a set of modules suitable for assembly at the user site within a suitable excavation. The unified design permits installation of all utilities service lines within a single one-time trench connecting the vault to each of one or several premises through a common service-entry module. The vault assembly enables utilities access within the vault for connecting main utilities lines to individual premises utilities line sets. Each utility can service its own lines within the vault connecting to each premises served. The individual vault modules include assembly and alignment and interface aids to resist lateral displacement forces and seal the vault against groundwater leakage.

Abstract: A semiconductor test device. In one embodiment, the test device includes a drill bit. The test device is configured to rotate the drill bit, at least after contacting the semiconductor device, for penetrating into the semiconductor device.

Abstract: A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test results or the status of the test modes are output from the chip. The method includes providing a chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another. A first serial bit string is stored, the bit sequence of which can be assigned to at least one test mode, in the first register set. A bit sequence is transmitted for application of the logical combination between the first register set and the second register set to the first bit string stored in the first register set. The test results are read out by means of a serial second bit string.

Abstract: An integrated memory includes a circuit for testing the operation of the memory, a register circuit is used for storing a bit combination, compression unit, to receive test data which have been read from the memory cells, and a memory unit to store a plurality of bits from a compressed bit fail map. Each of the bits is associated with a different address region. One of the bits registers an error data item within the associated address region. In addition, a decoder circuit is provided for receiving the compressed address and for accessing that bit in the memory unit, which is associated with a respective address region on the basis of the compressed address. A short evaluation time for a function test on the memory and flexible alignment with the individual memory size are made possible.

Abstract: A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers; programming the m different register groups by filling them with m first bit strings, each bit string being respectively assignable to a state of n test modes; transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and using a serial second bit string to read out test results or the status of the test modes.

Abstract: A test device for semiconductor devices is disclosed. One embodiment provides a probe card, having at least one contact test body for contacting a semiconductor device. The probe card includes self-alignment devices and/or a penetration restriction device, or parts thereof. A semiconductor device is provided having at least one contact field adapted to be contacted by contact test bodies of a test device. The semiconductor device includes self-alignment devices and/or a penetration restriction device, or parts thereof, for the contact test body in the region of the contact field.

Abstract: A device and method for electrical contacting for the testing of semiconductor devices is disclosed. One embodiment provides for the electrical connection of the semiconductor device with a test system, including devices for the contacting of connection pins or contact pads of the semiconductor device to be tested. The devices for the contacting of the connection pins or the contact pads of the semiconductor device to be tested include contact holders with at least one exchangeable contact tip.

Abstract: A device and method for determining target values for a parameter of a semiconductor device to be trimmed.

Abstract: A semiconductor component and method of testing a semiconductor component is disclosed. The invention relates to the parallel testing of semiconductor memory components having a fully functional memory area, which are classified as all good memory, and of semiconductor memory components having a restricted memory area, which are classified as partial good memory. For testing semiconductor memory components classified as partial good memory, the result, independently of the result of the comparison for those test addresses which are assigned to a memory area outside the functional memory area of the semiconductor memory component classified as partial good memory, is overwritten with an error free signal and a semiconductor memory component classified as all good memory is simulated. The testing of semiconductor memory components classified as partial good memory is accelerated and simplified.

Abstract: A semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories is disclosed. In one embodiment, in order to test the semiconductor memory components, test data are written to the memory cell array and, in parallel therewith, to a test write register. The data written to the memory cell array are compared bit by bit with the data stored in the test write register. An error free signal is generated in the case of matching. For semiconductor memory components classified as partial good memory, the result, independently of the result of the comparison for those data lines which are assigned to a memory area outside the functional memory area of the semiconductor memory component classified as partial good memory, is overwritten with an error free signal and a semiconductor memory component classified as all good memory is simulated.

Abstract: A method for compensation for a position change of a probe card is disclosed. In one embodiment, during the course of a functional test of an integrated circuit which is arranged on a semiconductor wafer includes determination of a temperature of the probe card and matching of the position of the semiconductor wafer to the temperature-dependent position change of the probe card. Matching of the position of the semiconductor wafer is carried out on the basis of the determined temperature and of a family of characteristics which reflects the temperature-dependent position change of the probe card.

Abstract: A semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories is disclosed. In one embodiment, in order to test the semiconductor memory components, test data are written to the memory cell array and, in parallel therewith, to a test write register. The data written to the memory cell array are compared bit by bit with the data stored in the test write register. An error free signal is generated in the case of matching. For semiconductor memory components classified as partial good memory, the result, independently of the result of the comparison for those data lines which are assigned to a memory area outside the functional memory area of the semiconductor memory component classified as partial good memory, is overwritten with an error free signal and a semiconductor memory component classified as all good memory is simulated.

Abstract: A semiconductor component and method of testing a semiconductor component is disclosed. The invention relates to the parallel testing of semiconductor memory components having a fully functional memory area, which are classified as all good memory, and of semiconductor memory components having a restricted memory area, which are classified as partial good memory. For testing semiconductor memory components classified as partial good memory, the result, independently of the result of the comparison for those test addresses which are assigned to a memory area outside the functional memory area of the semiconductor memory component classified as partial good memory, is overwritten with an error free signal and a semiconductor memory component classified as all good memory is simulated. The testing of semiconductor memory components classified as partial good memory is accelerated and simplified.

Abstract: A memory component and a method for the parallel testing of memory components are described herein. A fully functional memory area, which is classified herein as all good memory, and memory components including a restricted memory area, which are classified herein as partial good memory, are provided. Test data words composed of identical word sections are written to the memory cell array and are read out and compared bit by bit with a comparison data word. For partial good memory, a first word section of the test data word read out, for a memory area identified as irreparable, is overwritten by a second word section which is assigned to a different memory area. The assessed test data word is independent of the word section stored in the irreparable memory area. A memory component classified as all good memory is simulated. The testing of memory components classified as partial good memory is accelerated and simplified.

Abstract: To trim interface devices on semiconductor devices, such as trimmable output drivers and terminations, a measurement current produced in the test apparatus is impressed onto the interface device, and a measurement voltage produced by the measurement current in the interface device is detected by a trimming unit provided within the semiconductor device and is trimmed using control elements and trimming registers controlled by the trimming unit. To this end, the trimming unit ascertains trimming information which is stored in nonvolatile fashion in a memory unit in the semiconductor device and is loaded into the trimming registers in the semiconductor device whenever the semiconductor device is started up.

Abstract: The invention relates to a test arrangement for testing semiconductor circuit chips, in which a test signal received via a primary test channel from a driver amplifier of an item of test equipment is distributed via parallel sub-channels to a plurality of inputs of one or more semiconductor circuit chips under test the test arrangement having signal buffering circuits arranged in each sub-channel that receive and buffer the test signal from the driver amplifier before feeding it to the inputs of the semiconductor circuit chip(s).

Abstract: A method for testing semiconductor chips is disclosed. A chip to be tested has a test logic, at least one test mode is set in the form of a serial first bit string, the test modes are executed in the chip and test results or the status of the test modes are output from the chip in the form of a serial second bit string. The method includes at least one of the bit strings is provided with at least one binary check bit, the test logic being controlled by a check bit which is in a first logic state such that the bits of the bit string which follow the check bit are skipped until a check bit which is in the second logic state is detected by the test logic. The test logic is controlled by a check bit which is in the second logic state such that the bits of the bit string which follow the check bit are not skipped until a check bit which is in the first logic state is detected by the test logic.

Abstract: A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers; programming the m different register groups by filling them with m first bit strings, each bit string being respectively assignable to a state of n test modes; transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and using a serial second bit string to read out test results or the status of the test modes.

Abstract: A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test results or the status of the test modes are output from the chip. The method includes providing a chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another. A first serial bit string is stored, the bit sequence of which can be assigned to at least one test mode, in the first register set. A bit sequence is transmitted for application of the logical combination between the first register set and the second register set to the first bit string stored in the first register set. The test results are read out by means of a serial second bit string.

Abstract: A data memory to be tested is connected to a processing unit. Data items to be stored are produced from a test pattern data item in the processing unit and are stored in the data memory. The data memory is tested in that the test pattern data items are received from a test device, processed using a first function to form data items to be stored, and the data items are then stored. After the stored data items are read from the memory they are processed with a second function to form test data items whose number is once more smaller than the stored data items that are read from the memory.