Abstract: A memory device comprises a first port receiving a first register value and a second register value; a second port, receiving a third value; a first register being set to the first register value; a second register having an enabled status and a disabled status, the register being set to the second register value in the enabled status, the second register remaining unchanged in the disabled status; and a logic unit setting the status of the second register dependent on the first register value and the third value.

Abstract: A circuit configuration for adapting a logical address space of a processor unit to a physical address space of a memory includes, an interpretation unit, and data and control lines connecting the interpretation unit to the processor unit. The interpretation unit includes a register having a first register region and having a second register region to be written into by the processor unit. The interpretation unit continuously evaluates a logic state of the processor unit, writes contents of the second register region into the first register region at defined logic states and outputs contents of the first register region as an address. A linking unit is connected by address lines to the processor unit, to the interpretation unit and to the memory. The linking unit forms a total address for the memory from addresses transferred by the interpretation unit and the processor unit.