Abstract: A method is provided for operation a field effect transistor arrangement, the field effect transistor arrangement having a planar channel layer including a semiconductor material, a whole surface of an underside of the planar channel layer being applied to a top side of an electrically insulating substrate layer and an upper side of the planar channel layer being covered by an electrically insulating electrode insulation layer, the arrangement having a source electrode disposed by a first side edge of the planar channel layer and having a drain electrode disposed by a second side edge of the planar channel layer, and having a control electrode arranged above the planar channel layer between the source electrode and the drain electrode, wherein an adjusting electrode is arranged on an underside of the substrate layer, and a first contact region between the source electrode and the planar channel layer and a second contact region between the drain electrode and the planar channel layer are each a Schottky barri

Abstract: A field effect transistor arrangement having as planar channel layer comprises semiconductor material, the whole surface of the underside of the layer being applied to an upper side of an electrically insulating substrate layer and the upper side of the planar channel layer being covered by an insulation layer. The arrangement has a source electrode on a first side edge of the channel layer and a drain electrode on a second side edge of the channel layer and a control electrode arranged above the channel layer. An adjusting electrode is arranged on an underside of the substrate layer. A contact region between the source and drain electrodes and the planar channel layer is in each case configured as a midgap Schottky barrier. A respective barrier control electrode is arranged in the vicinity of the contact region of the source electrode and of the drain electrode, Each barrier control electrode can have a section that projects outwards in the direction of the planar channel layer.

Abstract: A doped region is provided on a substrate. A plane with conductive useful structures and a conductive filler structure is arranged at the surface of the substrate. The conductive filler structure is conductively connected to the doped region. In this way, charging of the conductive filler structure, which is provided for improving the planarity of the circuit arrangement and has no circuit-oriented function, is avoided.

Abstract: In the manufacture of CMOS devices, the n+ gate is partially counterdoped with boron to produce a modified p-type FET that has improved short channel effects, reduced gate induced drain leakage and gate oxide fields for improved reliability. A doped polysilicon layer is formed over a silicon or silicon oxide substrate, and is counterdoped with boron to a level of about 1×1013/cm2 to 5×1016/cm2 to adjust the work function but without changing the essentially n-type character of the gate electrode. This single counterdoping step achieves improved results for sub-micron devices below 0.5 micron at low cost. For CMOS device manufacturing, the alternating n-type and p-type devices are made in similar manner but reversing the n-type and p-type dopants.

Abstract: The MOS transistor has field plates and a subarea of the gate formed from the same polysilicon layer. A gate oxide lying underneath them is produced at the beginning of the fabrication process and it therefore exhibits particularly high quality. The polysilicon in the active area is raised to the same level as the adjoining field oxide areas, resulting in a planar topology.

Abstract: In a method for manufacturing an integrated circuit arrangement, trenches that define active zones are formed in a substrate. A first insulating layer that fills the narrow trenches is conformally deposited and is structured with a mask and anisotropic etching such that spacers arise at sidewalls of the wide trenches and supporting locations arise in a region of the wide trenches. The surface of the active zones is uncovered by forming a second insulating layer with an essentially planar surface and by a planarizing layer erosion on the basis of chemical-mechanical polishing or conventional dry etching.

Abstract: In order to produce an MOS transistor in an SOI substrate, the silicon layer (3), a gate dielectric (4) and an electrode layer (5) are structured in MESA fashion to form an active region. The flanks of the MESA structure (7) are provided with insulating spacers (8). In a further structuring step, a gate electrode (12) is formed from the electrode layer (5). The process provides a high packing density and at the same time avoids the problem of gate side-wall control as well as premature breakdown at oxide edges.

Abstract: In the manufacture of an MOS transistor in a substrate (1), source/drain zones (9) and a doped gate electrode (10) are simultaneously formed by drive-out from a doped layer (8). The dopant distribution in the source/drain zones (9) is set by a permeable diffusion barrier (7) at the surface of the source/drain zones (9). Over and above this, a dopant barrier (3'0 can be provided that prevents dopant from the gate electrode (10) from proceeding into the semiconductor substrate (1).

Abstract: A circuit structure having at least one MOS transistor whose source/drain regions are doped by a first conductivity type and whose gate electrode is doped by a conductivity type which is opposite to the first. The gate electrode has a lower dopant concentration at at least one of its edges than in its center. In the ON state, the gate electrode is driven to accumulation, with the result being that no gate depletion occurs. Such a circuit structure is also suitable for CMOS circuits containing PMOS transistors having an n-doped gate.

Abstract: In the manufacture of CMOS devices, the n+ gate is partially counterdoped with boron to produce a modified p-type FET that has improved short channel effects, reduced gate induced drain leakage and gate oxide fields for improved reliability. A doped polysilicon layer is formed over a silicon or silicon oxide substrate, and is counterdoped with boron to a level of about 1.times.10.sup.13 /cm.sup.2 to 5.times.10.sup.16 /cm.sup.2 to adjust the work function but without changing the essentially n-type character of the gate electrode. This single counterdoping step achieves improved results for sub-micron devices at low cost. For CMOS device manufacturing, the alternating n-type and p-type devices are made in similar manner but reversing the n-type and p-type dopants.

Abstract: In producing a CMOS circuit, an n-channel MOS transistor and a p-channel MOS transistor are formed in a semiconductor substrate. In situ p-doped, monocrystalline silicon structures are formed by epitaxial growth selectively with respect to insulating material and with respect to n-doped silicon, such silicon structures being suitable as a diffusion source for forming source/drain regions of the p-channel MOS transistor. The source/drain regions of the n-channel MOS transistor are produced beforehand by means of implantation or diffusion. Owing to the selectivity of the epitaxy that is used, it is not necessary to cover the n-doped source/drain regions of the n-channel MOS transistor during the production of the p-channel MOS transistor.

Abstract: In order to produce an integrated CMOS circuit, a dielectric layer and a silicon layer are applied to a substrate. During the formation of insulation structurers which insulate neighboring active regions in the substrate, the silicon layer is structured in such a way that it has separate sub-regions which are subsequently doped differently. By full-surface deposition of an electrically conductive layer and common structuring of the electrically conductive layer and the structured silicon layer differently doped gate electrodes and a metallization plane, by which the gate electrodes are electrically connected, are formed. Division of the silicon layer before doping prevents lateral dopant diffusion.

Abstract: In the production of a dual work function CMOS circuit, a polysilicon layer is produced for the purpose of forming a gate structure, the average grain diameter of which polysilicon layer is greater than the minimum extent in the gate structure, in order to suppress lateral dopant diffusion. In particular, a constriction having a width less than the average grain diameter is produced in the gate structure.

Abstract: Shallow junction field effect transistors are made by a low temperature process comprising ion implanting source/drain regions through a buffer layer in two steps, the first an ion implant at high dosage and low energy and the second an ion implant at low dosage and high energy. Ion implantation through the buffer layer avoids crystallographic damage to the silicon substrate. By grading the sidewall spacers of the gate electrode, more or fewer ions can be implanted through the spacer foot to ensure continuity between the source/drain regions and the channel region under the gate electrode.

Abstract: The MOS transistor has field plates and a subarea of the gate formed from the same polysilicon layer. A gate oxide lying underneath them is produced at the beginning of the fabrication process and it therefore exhibits particularly high quality. The polysilicon in the active area is raised to the same level as the adjoining field oxide areas, resulting in a planar topology.

Abstract: Deep submicran mosfets with defect enhanced CoSi2 formation and improved silicided junctions. A silicon wafer having a diffusion window is first precleaned with hydrofluoric acid. After the HF precleaning, the silicon wafer is transferred to a conventional cobalt sputtering tool where it is sputter cleaned by bombardment with low energy Ar+ions so as to form an ultra-shallow damage region. After the sputter cleaning, and without removing the wafer from the sputtering tool, Cobalt metal is deposited on the silicon wafer at room temperature and a CoSi2 layer is formed in the diffusion window.

Abstract: A method for producing a diffusion region adjacent to a recess in a substrate, with which structured diffusion regions can be produced within a recess is provided. The method is suitable, in particular, for producing diffusion regions of different conductivity type, which are arranged adjacent to one and the same recess or different recesses.

Abstract: A method for producing an insulating trench in an SOI substrate having integrated logic elements and high-voltage power components is provided. A trench extending down to an insulating layer is etched and covered with a doped silicon structure. Diffusion regions neighboring the trench are produced by drive-out from the doped amorphous silicon structure and an insulation structure is simultaneously produced in the trench by oxidation of the doped silicon structure.

Abstract: A MOSFET device utilizes the gate depletion effect to reduce the oxide field over the junction area. Since the gate depletion effect is present in the non-conducting off state for n.sup.+ gate PMOS devices and p.sup.+ gate NMOS devices, performance degradation is overcome. The level of doping of the gate is critical. In order to prevent gate depletion in the conducting, on state, the NMOS FET must use a highly doped n.sup.+ gate. The PMOS FET n.sup.+ gate must be non-degeneratively doped in order to utilize the advantage of the gate depletion in the non-conducting, off state. This is accomplished by implanting different doses of the same dopant type into the different gates. The MOSFET device can be implemented equally well for n.sup.+ gate PMOS FET devices as well as for p.sup.+ gate NMOS FET devices.

Abstract: A thin-film transistor has a doped polysilicon layer arranged at the surface of a substrate and has a polysilicon structure arranged on the doped polysilicon layer that is doped with the opposite conductivity type and that is limited by a sidewall is provided. The polysilicon structure has a source/drain region that is doped with the conductivity type of the doped polysilicon layer. A gate dielectric and a gate electrode thereon are arranged on the sidewall of the polysilicon structure between source/drain region and polysilicon layer, which likewise acts as source/drain region.