Abstract: A data acquisition system includes groups of transducers, a separate commutator for each group cyclically interrogates the transducers of the group. The resulting signal trains are separately decommutated and the data from each transducer group are stored in separate buffer systems. Each buffer system has a pair of buffers which alternate between reading and writing and a mask control selectively causes updating of the buffer content or copying from one into the other. A third buffer in each system is continuously updated. A formatting processor calls on all buffer pairs to assemble a PCM signal train in which the data from each transducer occur at least once in a cyclically repeated main frame. Buffer locations more frequently updated are called on more than once in the main frame. This processor is programmed to assemble the buffer addresses by counting up from starting addresses for a ROM that holds each buffer address once.