Abstract: A memory interface between the storage controller and memory card of an S/390 system uses the S/390 Storage Protect (SP) Key as an indication or protocol of storage command acceptance by the memory card. When the SP key is returned, then the command is deemed to be accepted by the memory card and the key will be used by the processor for its storage validation in accordance with the S/390 architecture. In the event that the memory card detected an error associated with the command, it will then return an error response code via a memory status bus. The memory status bus is multiplexed to service the existing architected requirement as well as an indicator of handshaking between the memory controller and the memory card.

Abstract: A high performance cache unit in a multiprocessing computer system comprises a shared level n cache 15 which is divided into a number of independently operated cache cores each of which containing a cache array for being used as buffer between plurality of processing units PU0-PU1 and a memory 18. Data requests and response requests issued by the processing units are separately executed in an interleaved mode to achieve a high degree of concurrency. For this purpose each cache core comprises arbitration circuits 101, 106 for an independent selection of pending data requests and response requests for execution. Selected data requests are identified by a cache directory lookup as linefetch-match or linefetch-miss operations and separately stored during their execution in operation registers 112, 114. Selected response requests are stored independently of the data requests in registers 105, 108, 109 and successively executed during free operation cycles which are not used by the execution of data requests.

Abstract: A multiprocessor computer system includes a system clock, a main memory connected through a memory bus to a microinstruction memory and a microinstruction decoder. Circuitry detects whether the microinstruction being decoded is the wrong microinstruction or has a parity error. On detection of such an erroneous microinstruction, the microinstruction is reloaded from the main memory into the microinstruction memory and then passed to the microinstruction decoder without interrupting the system clock or operation of the other processors.

Abstract: An improved multiple bus system for a multiprocessor computer system is disclosed for a computer system having a multiple level cache memory structure. The system includes one or more logical busses each including two or more physical busses for coupling multiple processors to a memory unit. Each logical bus is coupled to a bus switching unit which in turn couples all of the processors in the multiprocessor system to a memory unit over the physical busses comprising the logical bus. The system further manages near end signal reception problems caused by multiple processors electrically interconnected over such a bus system.

Abstract: A method and system for executing branch or other instructions in a loop. A loop end condition is evaluated in a fixed point unit while floating point instructions are evaluated in a floating point unit. In a first execution of the instructions in the loop, the loop end condition is processed as in prior art. A branch target instruction is stored in a branch target register and an instruction address of the branch target instruction is stored in a branch address register. However, on subsequent execution of the instructions in the loop, the branch condition is evaluated and, if it is fulfilled, once the end of the loop is detected by comparison of the effective address of the next instruction to be executed with the contents of the branch address register, the effective address of the first instruction in the loop is passed from the branch target register to an operations register.

Abstract: The invention concerns a multiprocessor system comprising processors PU0 to PUn and a common main memory. The memory is logically divided into at least two banks M0 and M1 and is interconnected with the processors by a bus 110. By means of control lines 111 to 118 a bus protocol is established so that one of said memory banks is accessed while another one of said banks is still busy.

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.