Patents by Inventor Ui-hui Kwon

Ui-hui Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200321334
    Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
  • Patent number: 10783306
    Abstract: A soft error rate (SER) associated with a design of a semiconductor circuit may be predicted based on implementing a simulation associated with the design. The simulation may include generating a simulation environment based on information indicating the design, performing a particle strike simulation based on the simulation environment to generate charge deposition information, and calculating a collected charge quantity from the charge deposition information. A determination may be made whether the SER predicted based on the collected charge quantity at least meets a threshold. The design may be modified, and the simulation repeated, if the predicted SER value meets a threshold value. A semiconductor circuit may be manufactured based on the design if the predicted SER value is less than the threshold value.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: September 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Udit Monga, Jong Wook Jeon, Ken Machida, Ui Hui Kwon
  • Patent number: 10714473
    Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
  • Patent number: 10700193
    Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyun Yoo, Ui-hui Kwon, Da-won Jeong, Jae-ho Kim, Jun-hyeok Kim, Kang-hyun Baek, Kyu-ok Lee
  • Publication number: 20200144411
    Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.
    Type: Application
    Filed: May 16, 2019
    Publication date: May 7, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyun YOO, Ui-hui Kwon, Da-won Jeong, Jae-ho Kim, Jun-hyeok Kim, Kang-hyun Baek, Kyu-ok Lee
  • Publication number: 20200066720
    Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
  • Patent number: 10529779
    Abstract: A method of manufacturing an image sensor that includes first and second semiconductor chips includes receiving manufacturing data respectively associated with the first and second semiconductor chips, processing the manufacturing data to determine a capacitance and a resistance of a pixel signal transmission line to which a pixel signal generated by each pixel of the plurality of pixels is transmitted, where the capacitance and the resistance corresponding to position information associated with each pixel of the plurality of pixels, and determining predicted characteristics of the image sensor based on the determined capacitance and resistance, prior to the first semiconductor chip being electrically connected to the second semiconductor chip. The first semiconductor chip may be electrically connected to the second semiconductor chip to form the image sensor based on a determination that the predicted characteristics of the image sensor at least meet a particular set of one or more target values.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yo-han Kim, Jong-wook Jeon, Ui-hui Kwon
  • Patent number: 10504894
    Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: December 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
  • Patent number: 10311187
    Abstract: A simulation method includes receiving a netlist describing a plurality of devices, performing an arithmetic operation by using values of random telegraph signal (RTS) noise factors respectively corresponding to the plurality of devices, generating an RTS model corresponding to each of the devices, based on a result of the arithmetic operation, and generating a netlist in which the RTS model is reflected.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: June 4, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Wook Jeon, Hyo-Eun Park, Keun-Ho Lee, Ui-Hui Kwon, Jong-Chol Kim
  • Publication number: 20190058010
    Abstract: A method of manufacturing an image sensor that includes first and second semiconductor chips includes receiving manufacturing data respectively associated with the first and second semiconductor chips, processing the manufacturing data to determine a capacitance and a resistance of a pixel signal transmission line to which a pixel signal generated by each pixel of the plurality of pixels is transmitted, where the capacitance and the resistance corresponding to position information associated with each pixel of the plurality of pixels, and determining predicted characteristics of the image sensor based on the determined capacitance and resistance, prior to the first semiconductor chip being electrically connected to the second semiconductor chip. The first semiconductor chip may be electrically connected to the second semiconductor chip to form the image sensor based on a determination that the predicted characteristics of the image sensor at least meet a particular set of one or more target values.
    Type: Application
    Filed: January 12, 2018
    Publication date: February 21, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yo-han KIM, Jong-wook JEON, Ui-hui KWON
  • Patent number: 10025888
    Abstract: A system for simulating a semiconductor device comprises a data input module configured to receive structural data of the semiconductor device comprising a first region and a second region, and a spatial discretization generating module configured to divide a space of the semiconductor device using the structural data through division of the first region into first type meshes and division of the second region into second type meshes different from the first type meshes.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: July 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ui-Hui Kwon, Vasily Zabelin, Sachio Nagura, Keun-Ho Lee
  • Patent number: 9966446
    Abstract: There is provided a semiconductor device to enhance operating characteristics by reducing parasitic capacitance between a gate electrode and other nodes.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: May 8, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Hee Park, Young Seok Song, Young Chul Hwang, Ui Hui Kwon, Keun Ho Lee, Jee Soo Chang, Jae Hee Choi
  • Publication number: 20180121587
    Abstract: A soft error rate (SER) associated with a design of a semiconductor circuit may be predicted based on implementing a simulation associated with the design. The simulation may include generating a simulation environment based on information indicating the design, performing a particle strike simulation based on the simulation environment to generate charge deposition information, and calculating a collected charge quantity from the charge deposition information. A determination may be made whether the SER predicted based on the collected charge quantity at least meets a threshold. The design may be modified, and the simulation repeated, if the predicted SER value meets a threshold value. A semiconductor circuit may be manufactured based on the design if the predicted SER value is less than the threshold value.
    Type: Application
    Filed: July 10, 2017
    Publication date: May 3, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Udit MONGA, Jong Wook Jeon, Ken Machida, Ui Hui Kwon
  • Publication number: 20170162568
    Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
    Type: Application
    Filed: December 6, 2016
    Publication date: June 8, 2017
    Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
  • Publication number: 20170154968
    Abstract: There is provided a semiconductor device to enhance operating characteristics by reducing parasitic capacitance between a gate electrode and other nodes.
    Type: Application
    Filed: November 16, 2016
    Publication date: June 1, 2017
    Inventors: YONG HEE PARK, YOUNG SEOK SONG, YOUNG CHUL HWANG, UI HUI KWON, KEUN HO LEE, JEE SOO CHANG, JAE HEE CHOI
  • Publication number: 20170103155
    Abstract: A simulation method includes receiving a netlist describing a plurality of devices, performing an arithmetic operation by using values of random telegraph signal (RTS) noise factors respectively corresponding to the plurality of devices, generating an RTS model corresponding to each of the devices, based on a result of the arithmetic operation, and generating a netlist in which the RTS model is reflected.
    Type: Application
    Filed: October 6, 2016
    Publication date: April 13, 2017
    Inventors: JONG-WOOK JEON, HYO-EUN PARK, KEUN-HO LEE, UI-HUI KWON, JONG-CHOL KIM
  • Publication number: 20170103154
    Abstract: A circuit design method includes extracting aging information of each of multiple devices from a netlist including one or more devices and a model library including information associated with a process variation. An arithmetic operation is performed using the information associated with the process variation and the aging information to calculate a deviation of the process variation of each device caused by aging. A netlist and/or a model library is extracted in which the calculated deviation is reflected.
    Type: Application
    Filed: August 30, 2016
    Publication date: April 13, 2017
    Inventors: JONG-WOOK JEON, JAE-HEE CHOI, YOO-HWAN KIM, KEUN-HO LEE, UI-HUI KWON, JONG-CHOL KIM
  • Patent number: 9466703
    Abstract: Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: October 11, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Hyun Song, Nak-Jin Son, Kwang-Seok Lee, Chang-Wook Jeong, Ui-Hui Kwon, Dong-Won Kim, Young-Kwan Park, Keun-Ho Lee
  • Publication number: 20150349094
    Abstract: Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region
    Type: Application
    Filed: December 31, 2014
    Publication date: December 3, 2015
    Inventors: Seung-Hyun SONG, Nak-Jin SON, Kwang-Seok LEE, Chang-Wook JEONG, Ui-Hui KWON, Dong-Won KIM, Young-Kwan PARK, Keun-Ho LEE
  • Publication number: 20140257784
    Abstract: A system for simulating a semiconductor device comprises a data input module configured to receive structural data of the semiconductor device comprising a first region and a second region, and a spatial discretization generating module configured to divide a space of the semiconductor device using the structural data through division of the first region into first type meshes and division of the second region into second type meshes different from the first type meshes.
    Type: Application
    Filed: January 13, 2014
    Publication date: September 11, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: UI-HUI KWON, VASILY ZABELIN, SACHIO NAGURA, KEUN-HO LEE