Patents by Inventor Ui-hui Kwon
Ui-hui Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230170351Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.Type: ApplicationFiled: January 17, 2023Publication date: June 1, 2023Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
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Patent number: 11581311Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.Type: GrantFiled: January 29, 2021Date of Patent: February 14, 2023Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
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Publication number: 20220406891Abstract: A semiconductor device includes a substrate, a gate electrode disposed on an upper surface of the substrate, a source region disposed on a first side of the gate electrode, a drain region disposed on a second side of the gate electrode opposite to the first side of the gate electrode in a horizontal direction, and an insulating structure at least partially buried inside the substrate on the substrate. The insulating structure includes a first portion disposed between the substrate and the gate electrode, and a second portion in contact with the drain region. An uppermost surface of the second portion of the insulating structure is lower than an uppermost surface of the first portion of the insulating structure. At least a part of the gate electrode is disposed on the uppermost surface of the second portion of the insulating structure.Type: ApplicationFiled: January 21, 2022Publication date: December 22, 2022Inventors: Jun Hyeok Kim, Jae-Hyun Yoo, Ui Hui Kwon, Kyu Ok Lee, Yong Woo Jeon, Da Won Jeong
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Publication number: 20210151433Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.Type: ApplicationFiled: January 29, 2021Publication date: May 20, 2021Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
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Patent number: 10950604Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.Type: GrantFiled: June 23, 2020Date of Patent: March 16, 2021Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Choi Kim, Chang Wook Jeong
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Publication number: 20200321334Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.Type: ApplicationFiled: June 23, 2020Publication date: October 8, 2020Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
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Patent number: 10783306Abstract: A soft error rate (SER) associated with a design of a semiconductor circuit may be predicted based on implementing a simulation associated with the design. The simulation may include generating a simulation environment based on information indicating the design, performing a particle strike simulation based on the simulation environment to generate charge deposition information, and calculating a collected charge quantity from the charge deposition information. A determination may be made whether the SER predicted based on the collected charge quantity at least meets a threshold. The design may be modified, and the simulation repeated, if the predicted SER value meets a threshold value. A semiconductor circuit may be manufactured based on the design if the predicted SER value is less than the threshold value.Type: GrantFiled: July 10, 2017Date of Patent: September 22, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Udit Monga, Jong Wook Jeon, Ken Machida, Ui Hui Kwon
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Patent number: 10714473Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.Type: GrantFiled: November 1, 2019Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
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Patent number: 10700193Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.Type: GrantFiled: May 16, 2019Date of Patent: June 30, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-hyun Yoo, Ui-hui Kwon, Da-won Jeong, Jae-ho Kim, Jun-hyeok Kim, Kang-hyun Baek, Kyu-ok Lee
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Publication number: 20200144411Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.Type: ApplicationFiled: May 16, 2019Publication date: May 7, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-hyun YOO, Ui-hui Kwon, Da-won Jeong, Jae-ho Kim, Jun-hyeok Kim, Kang-hyun Baek, Kyu-ok Lee
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Publication number: 20200066720Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.Type: ApplicationFiled: November 1, 2019Publication date: February 27, 2020Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
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Patent number: 10529779Abstract: A method of manufacturing an image sensor that includes first and second semiconductor chips includes receiving manufacturing data respectively associated with the first and second semiconductor chips, processing the manufacturing data to determine a capacitance and a resistance of a pixel signal transmission line to which a pixel signal generated by each pixel of the plurality of pixels is transmitted, where the capacitance and the resistance corresponding to position information associated with each pixel of the plurality of pixels, and determining predicted characteristics of the image sensor based on the determined capacitance and resistance, prior to the first semiconductor chip being electrically connected to the second semiconductor chip. The first semiconductor chip may be electrically connected to the second semiconductor chip to form the image sensor based on a determination that the predicted characteristics of the image sensor at least meet a particular set of one or more target values.Type: GrantFiled: January 12, 2018Date of Patent: January 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Yo-han Kim, Jong-wook Jeon, Ui-hui Kwon
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Patent number: 10504894Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.Type: GrantFiled: December 6, 2016Date of Patent: December 10, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
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Patent number: 10311187Abstract: A simulation method includes receiving a netlist describing a plurality of devices, performing an arithmetic operation by using values of random telegraph signal (RTS) noise factors respectively corresponding to the plurality of devices, generating an RTS model corresponding to each of the devices, based on a result of the arithmetic operation, and generating a netlist in which the RTS model is reflected.Type: GrantFiled: October 6, 2016Date of Patent: June 4, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Wook Jeon, Hyo-Eun Park, Keun-Ho Lee, Ui-Hui Kwon, Jong-Chol Kim
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Publication number: 20190058010Abstract: A method of manufacturing an image sensor that includes first and second semiconductor chips includes receiving manufacturing data respectively associated with the first and second semiconductor chips, processing the manufacturing data to determine a capacitance and a resistance of a pixel signal transmission line to which a pixel signal generated by each pixel of the plurality of pixels is transmitted, where the capacitance and the resistance corresponding to position information associated with each pixel of the plurality of pixels, and determining predicted characteristics of the image sensor based on the determined capacitance and resistance, prior to the first semiconductor chip being electrically connected to the second semiconductor chip. The first semiconductor chip may be electrically connected to the second semiconductor chip to form the image sensor based on a determination that the predicted characteristics of the image sensor at least meet a particular set of one or more target values.Type: ApplicationFiled: January 12, 2018Publication date: February 21, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Yo-han KIM, Jong-wook JEON, Ui-hui KWON
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Patent number: 10025888Abstract: A system for simulating a semiconductor device comprises a data input module configured to receive structural data of the semiconductor device comprising a first region and a second region, and a spatial discretization generating module configured to divide a space of the semiconductor device using the structural data through division of the first region into first type meshes and division of the second region into second type meshes different from the first type meshes.Type: GrantFiled: January 13, 2014Date of Patent: July 17, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ui-Hui Kwon, Vasily Zabelin, Sachio Nagura, Keun-Ho Lee
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Patent number: 9966446Abstract: There is provided a semiconductor device to enhance operating characteristics by reducing parasitic capacitance between a gate electrode and other nodes.Type: GrantFiled: November 16, 2016Date of Patent: May 8, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Hee Park, Young Seok Song, Young Chul Hwang, Ui Hui Kwon, Keun Ho Lee, Jee Soo Chang, Jae Hee Choi
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Publication number: 20180121587Abstract: A soft error rate (SER) associated with a design of a semiconductor circuit may be predicted based on implementing a simulation associated with the design. The simulation may include generating a simulation environment based on information indicating the design, performing a particle strike simulation based on the simulation environment to generate charge deposition information, and calculating a collected charge quantity from the charge deposition information. A determination may be made whether the SER predicted based on the collected charge quantity at least meets a threshold. The design may be modified, and the simulation repeated, if the predicted SER value meets a threshold value. A semiconductor circuit may be manufactured based on the design if the predicted SER value is less than the threshold value.Type: ApplicationFiled: July 10, 2017Publication date: May 3, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Udit MONGA, Jong Wook Jeon, Ken Machida, Ui Hui Kwon
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Publication number: 20170162568Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.Type: ApplicationFiled: December 6, 2016Publication date: June 8, 2017Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
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Publication number: 20170154968Abstract: There is provided a semiconductor device to enhance operating characteristics by reducing parasitic capacitance between a gate electrode and other nodes.Type: ApplicationFiled: November 16, 2016Publication date: June 1, 2017Inventors: YONG HEE PARK, YOUNG SEOK SONG, YOUNG CHUL HWANG, UI HUI KWON, KEUN HO LEE, JEE SOO CHANG, JAE HEE CHOI