Patents by Inventor Ui-Hyoung Lee
Ui-Hyoung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230058819Abstract: A method for fabricating a semiconductor device includes forming a mold structure on a substrate, the mold structure including inter-electrode insulating films and sacrificial films alternately and repeatedly stacked in a first direction, forming a channel hole which penetrates the mold structure in the first direction, forming a vertical channel structure inside the channel hole, removing the sacrificial films to form trenches which expose the vertical channel structure, the trenches extending in a second direction perpendicular to the first direction, and forming metallic lines which fill the trenches, respectively, each of the metallic lines being formed as a single layer, using a wet deposition process.Type: ApplicationFiled: March 30, 2022Publication date: February 23, 2023Inventors: Ui Hyoung LEE, Hyun Jun AHN, Ho Nyun PARK, Jong Seok LEE
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Patent number: 9082680Abstract: The inventive concept provides methods for inhibiting the formation of one or more oxides on metal bumps during the formation of solder joint structures and solder joint structures including one or more preservative films. In some embodiments, the solder joint structure includes a metal bump having a preservative film disposed on the surface thereof.Type: GrantFiled: June 28, 2012Date of Patent: July 14, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Il Choi, Jeong-Gi Jin, Ui-Hyoung Lee, Hyung-Seok Kim, Jeong-Woo Park
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Patent number: 8710657Abstract: Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.Type: GrantFiled: September 23, 2011Date of Patent: April 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-woo Park, Moon-gi Cho, Ui-hyoung Lee, Sun-hee Park
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Publication number: 20130256876Abstract: A semiconductor package includes a semiconductor chip having a plurality of contact pads on a surface thereof, a plurality of main bumps on the contact pads, respectively. Each of the plurality of main bumps includes a first pillar layer on one of the contact pads and a first solder layer on the first pillar layer, and the first solder layer includes an upper portion having an overhang portion.Type: ApplicationFiled: January 3, 2013Publication date: October 3, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ui-hyoung LEE, Moon-gi CHO, Mi-seok PARK, Sun-hee PARK, Hwan-sik LIM, Jin-ho CHOI, Fujisaki ATSUSHI
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Publication number: 20130000978Abstract: The inventive concept provides methods for inhibiting the formation of one or more oxides on metal bumps during the formation of solder joint structures and solder joint structures including one or more preservative films. In some embodiments, the solder joint structure includes a metal bump having a preservative film disposed on the surface thereof.Type: ApplicationFiled: June 28, 2012Publication date: January 3, 2013Inventors: Ju-Il Choi, Jeong-Gi Jin, Ui-Hyoung Lee, Hyung-Seok Kim, Jeong-Woo Park
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Publication number: 20120292195Abstract: An apparatus for electroplating a semiconductor device includes a plating bath accommodating a plating solution, and a paddle in the plating bath, the paddle including a plurality of holes configured to pass the plating solution through the paddle toward a substrate, and a plating solution flow reinforcement portion configured to selectively reinforce a flow of the plating solution to a predetermined area of the substrate, the predetermined area of the substrate being an area requiring a relatively increased supply of metal ions of the plating solution.Type: ApplicationFiled: April 3, 2012Publication date: November 22, 2012Inventors: Ui Hyoung LEE, Ju-Il Choi, Jae-Hyun Phee, Dong Hyeon Jang, Jeong-Woo Park
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METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MANUFACTURED USING THE SAME
Publication number: 20120129333Abstract: Provided are a method for manufacturing a semiconductor package and a semiconductor package manufactured using the method. The method includes providing a substrate having a first region and a second region having a higher step difference than the first region, i.e., having a difference in height, forming a mask pattern having a first opening exposing a portion of the first region and a second opening exposing a portion of the second region on the substrate, forming first and second bump material films filling the first and second openings, respectively, and forming the first and second bumps by performing a reflow process on the first and second bump material films, wherein the first opening has a lower portion having the same width with the second opening and a top portion having a width greater than the second opening.Type: ApplicationFiled: September 23, 2011Publication date: May 24, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ha-Young YIM, Eun-Chul AHN, Ui-Hyoung LEE, Moon-Gi CHO, Hwan-Sik LIM -
Patent number: 8183673Abstract: A microelectronic device structure as provided herein includes a conductive via having a body portion extending into a substrate from an upper surface thereof and a connecting portion laterally extending along the upper surface of the substrate. The connecting portion includes a recess therein opposite the upper surface of the substrate. The recess is confined within the connecting portion of the conductive via and does not extend beneath the upper surface of the substrate. A microelectronic device structure is also provided that includes a conductive via having a body portion extending into a substrate from an upper surface thereof and an end portion below the upper surface of the substrate. The end portion has a greater width than that of the body portion. A solder wettable layer is provided on the end portion. The solder wettable layer is formed of a material having a greater wettability with a conductive metal than that of the end portion of conductive via.Type: GrantFiled: September 24, 2009Date of Patent: May 22, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Son-Kwan Hwang, Keum-Hee Ma, Seung-Woo Shin, Min-Seung Yoon, Jong-Ho Yun, Ui-Hyoung Lee
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Publication number: 20120086123Abstract: Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.Type: ApplicationFiled: September 23, 2011Publication date: April 12, 2012Inventors: JEONG-WOO PARK, MOON-GI CHO, UI-HYOUNG LEE, SUN-HEE PARK
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Patent number: 8114772Abstract: A method of manufacturing semiconductor device includes preparing a substrate having a first surface and a second surface opposite to the first surface. A first insulation layer is formed on the second surface. A sacrificial layer is formed on the first insulation layer. An opening is formed to penetrate through the substrate and extend from the first surface to a portion of the sacrificial layer. A second insulation layer is formed on an inner wall of the opening. A plug is formed to fill the opening. The sacrificial layer is removed to expose a lower portion of the plug through the second surface.Type: GrantFiled: October 18, 2010Date of Patent: February 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Ha Lee, Min-Seung Yoon, Ui-Hyoung Lee, Ju-Ii Choi, Nam-Seog Kim, Keum-Hee Ma
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Publication number: 20110097891Abstract: A method of manufacturing semiconductor device includes preparing a substrate having a first surface and a second surface opposite to the first surface. A first insulation layer is formed on the second surface. A sacrificial layer is formed on the first insulation layer. An opening is formed to penetrate through the substrate and extend from the first surface to a portion of the sacrificial layer. A second insulation layer is formed on an inner wall of the opening. A plug is formed to fill the opening. The sacrificial layer is removed to expose a lower portion of the plug through the second surface.Type: ApplicationFiled: October 18, 2010Publication date: April 28, 2011Inventors: Kyu-Ha Lee, Min-Seung Yoon, Ui-Hyoung Lee, Ju-Il Choi, Nam-Seog Kim, Keum-Hee Ma
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Patent number: 7807337Abstract: An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.Type: GrantFiled: January 3, 2008Date of Patent: October 5, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo-Jong Lee, Hong-Seong Son, Ui-Hyoung Lee, Sang-Rok Hah, In-Ryong Kim, Yi-Gwon Kim
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Publication number: 20100096753Abstract: A microelectronic device structure as provided herein includes a conductive via having a body portion extending into a substrate from an upper surface thereof and a connecting portion laterally extending along the upper surface of the substrate. The connecting portion includes a recess therein opposite the upper surface of the substrate. The recess is confined within the connecting portion of the conductive via and does not extend beneath the upper surface of the substrate. A microelectronic device structure is also provided that includes a conductive via having a body portion extending into a substrate from an upper surface thereof and an end portion below the upper surface of the substrate. The end portion has a greater width than that of the body portion. A solder wettable layer is provided on the end portion. The solder wettable layer is formed of a material having a greater wettability with a conductive metal than that of the end portion of conductive via.Type: ApplicationFiled: September 24, 2009Publication date: April 22, 2010Inventors: Son-Kwan Hwang, Keum-Hee Ma, Seung-Woo Shin, Min-Seung Yoon, Jong-Ho Yun, Ui-Hyoung Lee
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Publication number: 20080102409Abstract: An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.Type: ApplicationFiled: January 3, 2008Publication date: May 1, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo-Jong LEE, Hong-Seong SON, Ui-Hyoung LEE, Sang-Rok HAH, In-Ryong KIM, Yi-Gwon Kim
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Publication number: 20070059923Abstract: Methods of fabricating an interconnection line in a semiconductor device and a semiconductor device including such an interconnection line. The method involves forming a lower interconnection line on a semiconductor substrate, forming a mold pattern that defines an opening through which the lower interconnection line is exposed, filling the opening with a conductive material to form a via, removing the mold pattern to make the via remain on the lower interconnection line, forming an interlevel dielectric (ILD) layer that covers the lower interconnection line and the via, patterning the ILD layer, exposing the via, forming a trench that defines a region in which an interconnection line is to be formed, and filling the trench to fabricate a damascene interconnection line connected to the via.Type: ApplicationFiled: June 2, 2006Publication date: March 15, 2007Inventors: Hyo-jong Lee, Ui-hyoung Lee, Hong-jae Shin, Nae-in Lee, Soo-geun Lee
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Publication number: 20050116317Abstract: An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.Type: ApplicationFiled: November 8, 2004Publication date: June 2, 2005Inventors: Hyo-Jong Lee, Hong-Seong Son, Ui-Hyoung Lee, Sang-Rok Hah, Il-Ryong Kim, Yi-Gwon Kim