Abstract: A neuromorphic memory circuit includes a plurality of memory cells, and each of the plurality of memory cells includes a first switching element having a threshold switching time determined based on a voltage applied to both ends of the first switching element at a time of receiving an input signal, and outputting the input signal in response to an elapse of the threshold switching time from a point in time at which the input signal is received; a first resistive memory element connected to the first switching element to divide the voltage applied to both ends of the first switching element; and a synapse circuit to generate an output signal in response to the input signal delayed by the threshold switching time.