Abstract: A modulator that quantizes a first signal into a quantized signal having a plurality of bits includes an integrator performing sampling on the first signal in a first period, and to integrate a difference between the first signal and a reference signal in a second period; and a quantizer receiving a second signal which is an output of the integrator and operating in synchronization with a first clock having a cycle shorter than the first period, the quantizer generating the quantized signal on the basis of the second signal in the first period and outputting the reference signal on the basis of the quantized signal to the integrator.

Abstract: A data modulation circuit has an adder adding an input signal, and an output signal of a memory device; and an output circuit part discriminating and quantizing the output signal of the adder by a predetermined threshold value. The memory device receives and holds the output signal of the adder and a predetermined signal, and supplies the held signals to the adder as an output signal of the memory device.

Abstract: A data modulation circuit has an adder adding an input signal, and an output signal of a memory device; and an output circuit part discriminating and quantizing the output signal of the adder by a predetermined threshold value. The memory device receives and holds the output signal of the adder and a predetermined signal, and supplies the held signals to the adder as an output signal of the memory device.

Abstract: A voltage comparing circuit activates a first voltage comparison signal when a control voltage is lower than a first reference voltage and a second voltage comparison signal when the control voltage is higher than a second reference voltage. In synchronization with a count clock, a counter decrements a counter value during activation of the first voltage comparison signal and increments the counter value during activation of the second voltage comparison signal. An oscillating circuit selects one of oscillation frequency bands by the counter value and regulates an oscillation frequency according to the control voltage within the selected oscillation frequency band to output an output clock. This makes it possible to secure a wide oscillation frequency range in response to variance in operating conditions or a reduction in a range of the control voltage and to regulate the oscillation frequency of the voltage controlled oscillator by the control voltage alone.

Abstract: A switch circuit shifts a bit number of a digital input signal sequentially according to a selection signal and outputs the shifted digital signal as a digital output signal. A switch control circuit receives a shift signal which changes to a random value, performs an operation on the bit number and a value indicated by the shift signal to generate a next bit number, and outputs the generated bit number as the selection signal. Since a random bit number is generated by the switch control circuit, the switch circuit can shift the bit number of the digital input signal in nonregular, random order and output the shifted digital signal as the digital output signal. By supplying the digital output signal to a D/A conversion part, D/A conversion accuracy can be improved.

Abstract: A switch circuit shifts a bit number of a digital input signal sequentially according to a selection signal and outputs the shifted digital signal as a digital output signal. A switch control circuit receives a shift signal which changes to a random value, performs an operation on the bit number and a value indicated by the shift signal to generate a next bit number, and outputs the generated bit number as the selection signal. Since a random bit number is generated by the switch control circuit, the switch circuit can shift the bit number of the digital input signal in nonregular, random order and output the shifted digital signal as the digital output signal. By supplying the digital output signal to a D/A conversion part, D/A conversion accuracy can be improved.

Abstract: A voltage comparing circuit activates a first voltage comparison signal when a control voltage is lower than a first reference voltage and a second voltage comparison signal when the control voltage is higher than a second reference voltage. In synchronization with a count clock, a counter decrements a counter value during activation of the first voltage comparison signal and increments the counter value during activation of the second voltage comparison signal. An oscillating circuit selects one of oscillation frequency bands by the counter value and regulates an oscillation frequency according to the control voltage within the selected oscillation frequency band to output an output clock. This makes it possible to secure a wide oscillation frequency range in response to variance in operating conditions or a reduction in a range of the control voltage and to regulate the oscillation frequency of the voltage controlled oscillator by the control voltage alone.

Abstract: An oversampling modulator device includes an adder outputting an signal indicating a sum of an input signal and a first delayed signal, the input signal having a plurality of bits, the output signal having upper bits included in a first signal and the remaining bits included in a second signal. A subtractor outputs a signal indicating a difference between the first signal and a second delayed signal. A first delay unit outputs the first delayed signal by delaying a third signal having upper bits produced by the subtraction signal and lower bits produced by the second signal. A quantizer performs quantization processing of the third signal and outputs a quantization signal having a predetermined number of bits. A second delay unit outputs the second delayed signal by delaying the quantization signal. The quantizer selects specific bits included in the third signal to generate the quantization signal.

Abstract: An oversampling modulator device includes an adder outputting an signal indicating a sum of an input signal and a first delayed signal, the input signal having a plurality of bits, the output signal having upper bits included in a first signal and the remaining bits included in a second signal. A subtractor outputs a signal indicating a difference between the first signal and a second delayed signal. A first delay unit outputs the first delayed signal by delaying a third signal having upper bits produced by the subtraction signal and lower bits produced by the second signal. A quantizer performs quantization processing of the third signal and outputs a quantization signal having a predetermined number of bits. A second delay unit outputs the second delayed signal by delaying the quantization signal. The quantizer selects specific bits included in the third signal to generate the quantization signal.

Abstract: The compressed image data ZZ includes code data representing a quantization level coefficient QCx inserted between block data units. DCT coefficients QF(u,v) and a quantization level coefficient QCx, which are decoded form the compressed image data ZZ, are multiplied in the inverse quantization table generator 250 to generate a quantization table QT, and the inverse quantization unit 250 executes inverse quantization with the quantization table QT. Since the quantization level coefficient QCx is inserted between block data units in the compressed image data, the quantization table QT is renewed every time when a new quantization level coefficient QCx is decoded. The compressed image data also includes a special type of data, or null run data, representing a series of pixel blocks having an identical image pattern.