Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.

Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.

Abstract: A method of manufacturing an image sensor that includes first and second semiconductor chips includes receiving manufacturing data respectively associated with the first and second semiconductor chips, processing the manufacturing data to determine a capacitance and a resistance of a pixel signal transmission line to which a pixel signal generated by each pixel of the plurality of pixels is transmitted, where the capacitance and the resistance corresponding to position information associated with each pixel of the plurality of pixels, and determining predicted characteristics of the image sensor based on the determined capacitance and resistance, prior to the first semiconductor chip being electrically connected to the second semiconductor chip. The first semiconductor chip may be electrically connected to the second semiconductor chip to form the image sensor based on a determination that the predicted characteristics of the image sensor at least meet a particular set of one or more target values.

Abstract: A simulation method includes receiving a netlist describing a plurality of devices, performing an arithmetic operation by using values of random telegraph signal (RTS) noise factors respectively corresponding to the plurality of devices, generating an RTS model corresponding to each of the devices, based on a result of the arithmetic operation, and generating a netlist in which the RTS model is reflected.

Abstract: A method of manufacturing an image sensor that includes first and second semiconductor chips includes receiving manufacturing data respectively associated with the first and second semiconductor chips, processing the manufacturing data to determine a capacitance and a resistance of a pixel signal transmission line to which a pixel signal generated by each pixel of the plurality of pixels is transmitted, where the capacitance and the resistance corresponding to position information associated with each pixel of the plurality of pixels, and determining predicted characteristics of the image sensor based on the determined capacitance and resistance, prior to the first semiconductor chip being electrically connected to the second semiconductor chip. The first semiconductor chip may be electrically connected to the second semiconductor chip to form the image sensor based on a determination that the predicted characteristics of the image sensor at least meet a particular set of one or more target values.

Abstract: A system for simulating a semiconductor device comprises a data input module configured to receive structural data of the semiconductor device comprising a first region and a second region, and a spatial discretization generating module configured to divide a space of the semiconductor device using the structural data through division of the first region into first type meshes and division of the second region into second type meshes different from the first type meshes.

Abstract: A circuit design method includes extracting aging information of each of multiple devices from a netlist including one or more devices and a model library including information associated with a process variation. An arithmetic operation is performed using the information associated with the process variation and the aging information to calculate a deviation of the process variation of each device caused by aging. A netlist and/or a model library is extracted in which the calculated deviation is reflected.

Abstract: A simulation method includes receiving a netlist describing a plurality of devices, performing an arithmetic operation by using values of random telegraph signal (RTS) noise factors respectively corresponding to the plurality of devices, generating an RTS model corresponding to each of the devices, based on a result of the arithmetic operation, and generating a netlist in which the RTS model is reflected.

Abstract: Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region

Abstract: Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region

Abstract: A system for simulating a semiconductor device comprises a data input module configured to receive structural data of the semiconductor device comprising a first region and a second region, and a spatial discretization generating module configured to divide a space of the semiconductor device using the structural data through division of the first region into first type meshes and division of the second region into second type meshes different from the first type meshes.

Abstract: A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.

Abstract: A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.

Abstract: A filament member configured to discharge thermions may be employed in an ion source of an ion implantation apparatus. A filament member may include an anode disposed around a central portion of the filament member, a cathode disposed around a periphery of the filament and/or enclosing the anode, and at least one conductive path disposed between the anode and the cathode to discharge the thermions.

Abstract: A filament member configured to discharge thermions may be employed in an ion source of an ion implantation apparatus. A filament member may include an anode disposed around a central portion of the filament member, a cathode disposed around a periphery of the filament and/or enclosing the anode, and at least one conductive path disposed between the anode and the cathode to discharge the thermions.

Abstract: A filament member, ion source, and an ion implantation apparatus. The filament member may have a plate shape, and the thermoelectron emitter may include slots and a plurality of conductive paths disposed around the slots to emit thermoelectrons.

Abstract: Disclosed is a simulation method for determining wafer warpage. This method includes dividing layers and evaluating a composition ratio of materials composing the layers. The method mathematically transforms a semiconductor device, which is constructed as a complicated structure with various materials, into a simplified, mathematically equivalent stacked structure comprising a plurality of unit layer, and utilizes values of mechanical characteristics, which are obtained from the transformed layer structure, for estimating wafer warpage. As a result, it is possible to complete an operation of wafer warpage simulation using information about pattern density of the semiconductor device.

Abstract: The present invention can provide ion implanter devices including an arc chamber including at least a first inner region and a second inner region, an electron emitting device disposed in the arc chamber adjacent the first inner region and adapted to emit electrons, an electron returning device disposed in the arc chamber adjacent the second inner region and adapted to return at least some of the electrons emitted from the electron emitting device into the second inner region; and an electric field and magnetic field generating device adapted to provide a magnetic field to the arc chamber, wherein at least one inner wall of the arc chamber has a convex surface.

Abstract: The present invention can provide ion implanter devices including an arc chamber including at least a first inner region and a second inner region, an electron emitting device disposed in the arc chamber adjacent the first inner region and adapted to emit electrons, an electron returning device disposed in the arc chamber adjacent the second inner region and adapted to return at least some of the electrons emitted from the electron emitting device into the second inner region; and an electric field and magnetic field generating device adapted to provide a magnetic field to the arc chamber, wherein at least one inner wall of the arc chamber has a convex surface.