Abstract: A method of facilitating content selection includes generating benchmark queries for a particular category. Generating the benchmark queries includes applying a text prompt as input to a language model trained on a knowledge base. The text prompt requests search queries indicative of user interest in the particular category. The method also includes selecting, responsive to new search queries entered by users, content items associated with the particular category for delivery to client devices of the users. Selecting the content items includes determining whether the new search queries correspond to the particular category at least in part by comparing the new search queries to a query set that includes the benchmark queries.

Abstract: An apparatus includes: at least one core to execute instructions; an interface circuit coupled to the at least one core to perform non-processing operations and interface with one or more platform components; and a power controller coupled to the least one core and the interface circuit. The power controller is to receive at least one efficiency latency parameter to optimize a power-latency tradeoff and control a frequency of the interface circuit based at least in part on an activity level of the at least one core and the at least one efficiency latency parameter. Other embodiments are described and claimed.

Abstract: In an example, an apparatus includes: a proportional-integral-derivative (PID) controller to receive a first feedback signal and a second feedback signal, and determine, based at least in part on the first and second feedback signals, a first frequency; a circuit coupled to the PID controller to receive the determination of the first frequency and modify, based on at least one limit signal, the first frequency to a working point frequency and provide the working point frequency to at least one core to cause the at least one core to operate at the working point frequency; and a tracking error circuit coupled to the PID controller to receive the determination of the first frequency and an indication of the working point frequency and determine therefrom the second feedback signal, and provide the second feedback signal to the PID controller.

Abstract: Techniques and mechanisms for determining an operational state of a processor with inference engine circuitry. In an embodiment, inference engine circuitry implements a classification function with which a given workload is classified as belonging to any of multiple possible workload classes. Each of the workload classes corresponds to a different respective value of an uncore-core frequency ratio. The inference engine circuitry receives or otherwise identifies telemetry information which is generated during a particular phase of the workload execution. Based on the telemetry information, the inference engine circuitry generates an output specifying or otherwise indicating a recommended frequency ratio value which corresponds to an identified workload class. In another embodiment, a frequency of a core, or a frequency of uncore resource, is changed based on the recommended frequency ratio value.

Abstract: A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Abstract: A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.

Abstract: A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Abstract: A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.

Abstract: Systems and methods for flexible hybrid electronic (FHE) systems integrate traditional rigid integrated circuits with flexible substrates and/or interconnects. The layout and components of the system may be selected and/or optimized for a desired level of performance or flexibility. Via use of exemplary FHE system principles, improved wearable devices and other portable electronic systems may be realized.

Abstract: Systems and methods for flexible hybrid electronic (FHE) systems integrate traditional rigid integrated circuits with flexible substrates and/or interconnects. The layout and components of the system may be selected and/or optimized for a desired level of performance or flexibility. Via use of exemplary FHE system principles, improved wearable devices and other portable electronic systems may be realized.