Patents by Inventor Ujjwal Gupta

Ujjwal Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11809250
    Abstract: A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Ali Mohammad, Asma Al-Rawi, Ujjwal Gupta, Federico Ardanaz, Jonathan Eastep
  • Publication number: 20230236651
    Abstract: A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.
    Type: Application
    Filed: June 26, 2020
    Publication date: July 27, 2023
    Inventors: UJJWAL GUPTA, ANKUSH VARMA, LAKSHMIPRIYA SESHAN, NIKETHAN SHIVANAND BALIGAR, NIKHIL GUPTA, SWADESH CHOUDHARY, YOGESH BANSAL
  • Publication number: 20220100247
    Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.
    Type: Application
    Filed: September 26, 2020
    Publication date: March 31, 2022
    Applicant: Intel Corporation
    Inventors: Vivek Garg, Ankush Varma, Krishnakanth Sistla, Nikhil Gupta, Nikethan Shivanand Baligar, Stephen Wang, Nilanjan Palit, Timothy Kam, Adwait Purandare, Ujjwal Gupta, Stanley Chen, Dorit Shapira, Shruthi Venugopal, Suresh Chemudupati, Rupal Parikh, Eric Dehaemer, Pavithra Sampath, Phani Kumar Kandula, Yogesh Bansal, Dean Mulla, Michael Tulanowski, Stephen Haake, Andrew Herdrich, Ripan Das
  • Publication number: 20210124404
    Abstract: A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 29, 2021
    Applicant: Intel Corporation
    Inventors: Ali Mohammad, Asma Al-Rawi, Ujjwal Gupta, Federico Ardanaz, Jonathan Eastep
  • Patent number: 9984962
    Abstract: Systems and methods for flexible hybrid electronic (FHE) systems integrate traditional rigid integrated circuits with flexible substrates and/or interconnects. The layout and components of the system may be selected and/or optimized for a desired level of performance or flexibility. Via use of exemplary FHE system principles, improved wearable devices and other portable electronic systems may be realized.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: May 29, 2018
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Umit Y. Ogras, Ujjwal Gupta, Md Ali Muztoba
  • Publication number: 20170062309
    Abstract: Systems and methods for flexible hybrid electronic (FHE) systems integrate traditional rigid integrated circuits with flexible substrates and/or interconnects. The layout and components of the system may be selected and/or optimized for a desired level of performance or flexibility. Via use of exemplary FHE system principles, improved wearable devices and other portable electronic systems may be realized.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 2, 2017
    Inventors: Umit Y. Ogras, Ujjwal Gupta, Md Ali Muztoba