Abstract: A system for improving video coding performance while using a merge mode in motion estimation. The system comprises a processor configured to perform one or more refinement searches on a plurality of candidate regions of a current frame, wherein the plurality of candidate regions comprises a candidate region identified in a reference frame and a plurality of candidate search regions, and wherein the one or more refinement searches reduce the plurality of candidate regions to obtain reduced candidates.

Abstract: Instructions embedded on a computer-readable medium, when executed on one or more computer devices, improve video coding performance while using a merge mode in motion estimation. The instructions comprise instructions to perform one or more refinement searches on a plurality of candidate regions of a current frame. The instructions also comprise instructions to determine one or more distortion values based, at least in part, on reduced candidate regions and instructions to code motion data based, at least in part, on the one or more refinement searches.

Abstract: Instructions embedded on a computer-readable medium, when executed on one or more computer devices, improve video coding performance while using a merge mode in motion estimation. The instructions comprise instructions to perform one or more refinement searches on a plurality of candidate regions of a current frame. The instructions also comprise instructions to determine one or more distortion values based, at least in part, on reduced candidate regions and instructions to code motion data based, at least in part, on the one or more refinement searches.

Abstract: A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.

Abstract: A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.

Abstract: A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.

Abstract: A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.

Abstract: A method operates within an integrated circuit device having a plurality of processing lanes. The method determines a first number of packs among one or more first packs associated with a first processing lane of the plurality of processing lanes, associates the first number of packs with a first used field of the first processing lane, determines a second number of packs among one or more second packs associated with a second processing lane of the plurality of processing lanes, and associates the second number of packs with a second used field of the second processing lane.

Abstract: A method operates within an integrated circuit device having a plurality of processing lanes. The method determines a first number of packs among one or more first packs associated with a first processing lane of the plurality of processing lanes, associates the first number of packs with a first used field of the first processing lane, determines a second number of packs among one or more second packs associated with a second processing lane of the plurality of processing lanes, and associates the second number of packs with a second used field of the second processing lane.

Abstract: A method of operation within an integrated circuit device having a plurality of processing lanes. A first sub-stream of data, having a variable length, is generated in a first one of the processing lanes. A second sub-stream of data, also having a variable length, is generated in a second one of the processing lanes. The first and second sub-streams are then output to form a single bitstream.

Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.

Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.

Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.

Abstract: Disclosed are methods and systems for dynamically determining data-transfer paths. The data-transfer paths are dynamically determined in response to an instruction that facilitates data transfer among execution lanes in an integrated-circuit processing device operable to execute operations in parallel. In addition, embodiments include an integrated-circuit processing device operable to execute operations in parallel, including the capability of providing confirmation information to potential source lanes, the confirmation information indicating whether the potential source lanes may send data to requested destination lanes during a data-transfer interval.

Abstract: A method of estimating motion is disclosed. A first plurality of candidates is identified in a reference frame, wherein the total area occupied by the first plurality of candidates is substantially smaller than that of the reference frame. A first refinement search is then performed based, at least in part, on the first plurality of candidates. One or more best candidates are then identified based, at least in part, on the first refinement search. Finally, motion data is encoded based, at least in part, on the one or more best candidates.

Abstract: Disclosed are methods and systems for dynamically determining data-transfer paths. The data-transfer pats are determined in response to an instruction that facilitates data transfer among execution lanes in an integrated-circuit processing device operable to execute operations in parallel.

Abstract: A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes.

Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image IS disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.

Abstract: A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full processor efficiency without cycles wasted due to branch latency. Data to be processed are divided into two groups based on whether or not they satisfy a given condition by e.g., steering each to one of the two index vectors. Once the data have been segregated in this way, subsequent processing can be performed without conditional operations, processor cycles wasted due to branch latency, incorrect speculation or execution of unnecessary instructions due to predication. Other examples of conditional operations include combining one or more input vectors into a single output vector based on a condition vector, conditional vector switching, conditional vector combining, and conditional vector load balancing.

Abstract: A processor having a zero-overhead operand copy capability. The processor includes multiple execution units to execute instructions in parallel and multiple register files each associated with one or more of the execution units. The processor further includes circuitry to select either an instruction execution result from a first one of the execution units or content of a register within a first one of the register files associated with the first one of the execution units to be stored within a register within a second one of the register files.