Abstract: In one example, an apparatus comprises: a first switch and a second switch coupled between a fuse terminal and a ground terminal, the first switch having a first switch control terminal, the second switch having a second switch control terminal; and a driver circuit having a control input, a first control output, and a second control output, the control input coupled to the fuse terminal, the first control output coupled to the first switch control terminal, and the second control output coupled to the second switch control terminal.

Abstract: A circuit includes a first driver, a second driver, and a bias generator. First driver has a first bias terminal, a first reference terminal, a first driver input, and a first driver output. The second driver has a second bias terminal, a second reference terminal, a second driver input, and a second driver output. The bias generator has a first input, a second input, a first bias output, and a second bias output, the first input coupled to the first reference terminal, the second input coupled to the second reference terminal, the first bias output coupled to the first bias terminal, and the second bias output coupled to the second bias terminal, wherein the bias generator is configurable to generate, based on a supply voltage, a first bias voltage at the first bias output and a second bias voltage at the second bias output.

Abstract: In one example, a bidirectional switch driver includes a first driver circuit and a second driver circuit having inputs coupled to a control input of the bidirectional switch driver, the first driver circuit has a first driver output and a first reference terminal, and the second driver circuit has a second driver output and a second reference terminal. The first driver circuit is configured to, responsive to the control input, provide a first voltage difference or a second voltage difference between the first driver output and the first reference terminal. The second driver circuit is configured to, responsive to the control input, provide a third voltage difference between the second driver output and the second reference terminal, a magnitude of the third voltage difference being between respective magnitudes of the first and second voltage differences.

Abstract: In one example, an apparatus comprises a bidirectional switch substrate bias circuit. The bidirectional switch substrate bias circuit comprises: a first switch coupled between a substrate bias terminal and a first switch current terminal, the first switch having a first switch control terminal; a second switch coupled between the substrate bias terminal and a second switch current terminal, the second switch having a second switch control terminal; and a control circuit having first and second inputs and first and second outputs, the first and second inputs coupled to the respective first and second switch current terminals, and the first and second outputs coupled to the respective first and second switch control terminals, the control circuit configured to, responsive to respective states of the first and second inputs, enable one of the first or second switches and disable the other one of the first or second switches.

Abstract: A semiconductor device includes a semiconductor substrate; a source electrode, a gate electrode, and a drain electrode on the semiconductor substrate; a staircase dielectric structure on the semiconductor substrate and laterally between the gate electrode and the drain electrode; and a metal layer on the staircase dielectric structure. The staircase dielectric structure includes a first dielectric layer on the semiconductor substrate, a first etch-stop layer on the first dielectric layer, and a second dielectric layer on the first etch-stop layer, where the first dielectric layer has a first lateral dimension greater than a second lateral dimension of the second dielectric layer. The metal layer includes a first field plate on at least a first region of the first dielectric layer and a second field plate on at least a second region of the second dielectric layer.

Abstract: The present disclosure generally relates to semiconductor devices in an integrated circuit (IC) that have different threshold voltages. In an example, an IC includes a semiconductor substrate, a channel layer, a barrier layer, a first semiconductor device, and a second semiconductor device. The channel layer is on the semiconductor substrate, and the channel layer includes a gallium nitride (GaN) material. The barrier layer is on the channel layer. The first semiconductor device is on the semiconductor substrate. The first semiconductor device includes a first terminal over the barrier layer, and the first semiconductor device has a first threshold voltage. The second semiconductor device is on the semiconductor substrate. The second semiconductor device includes a second terminal over the barrier layer, and the second semiconductor device has a second threshold voltage different from the first threshold voltage. The first and second threshold voltages are both positive or negative voltages.

Abstract: The present disclosure generally relates to semiconductor devices in an integrated circuit (IC) that have different threshold voltages. In an example, a channel layer is formed on a semiconductor substrate. The channel layer includes a gallium nitride (GaN) material. A barrier layer is formed on the channel layer. A first semiconductor device is formed on the semiconductor substrate. The first semiconductor device includes a first terminal over the barrier layer, and the first semiconductor device has a first threshold voltage. A second semiconductor device is formed on the semiconductor substrate. The second semiconductor device includes a second terminal over the barrier layer, and the second semiconductor device has a second threshold voltage different from the first threshold voltage. The first and second threshold voltages are both positive or negative voltages.

Abstract: A semiconductor device, such as a GaN-based high electron mobility transistor (HEMT), includes a hybrid drain contact structure over a channel layer and a barrier layer. The hybrid drain contact structure includes a first drain contact electrically coupled to the channel layer, a semiconductor layer over the barrier layer and including a first semiconductor portion and a second semiconductor portion, and a second drain contact on the semiconductor layer and electrically coupled to the first drain contact. The second drain contact includes a first metal portion and a second metal portion. The first metal portion and the first semiconductor portion form a first junction having a first energy barrier height. The second metal portion and the second semiconductor portion form a second junction having a second energy barrier height lower than the first energy barrier height.

Abstract: A semiconductor device includes a substrate, a semiconductor layer stack on the substrate, and a gate, a source, and a drain formed on or in the semiconductor layer stack. The semiconductor layer stack may include a non-silicon channel layer and a barrier layer on the channel layer. At least one of the substrate or the semiconductor layer stack includes a diode, a first terminal of the diode electrically coupled to the source, and a second terminal of the diode electrically coupled to the drain.

Abstract: The present disclosure generally relates to semiconductor processing for a self-aligned gate structure and corresponding semiconductor device. In an example, a semiconductor device includes a semiconductor substrate, a semiconductor gate layer, an offset dielectric layer, and a gate metal contact. The semiconductor gate layer is over the semiconductor substrate. The offset dielectric layer is over the semiconductor gate layer. The gate metal contact is over the offset dielectric layer and is through an opening through the offset dielectric layer. The gate metal contact contacts the semiconductor gate layer through the opening through the offset dielectric layer. A first sidewall of the semiconductor gate layer, a second sidewall of the offset dielectric layer, and a third sidewall of the gate metal contact are vertically aligned over the semiconductor substrate.

Abstract: The present disclosure generally relates to a semiconductor device having a slanted field plate. In an example, a semiconductor device includes a semiconductor substrate, a gate, a drain contact, a source contact, and a field plate. The gate is on a surface of the semiconductor substrate. The drain contact and a source contact are on the semiconductor substrate. The field plate is over the surface of the semiconductor substrate and extends from one side of the gate towards the drain contact. The field plate includes multiple field plate portions. Each of the multiple field plate portions has a uniform respective slope with respect to the surface, and the multiple field plate portions have different slopes.

Abstract: The present disclosure generally relates to a conductive layer in a gate structure of a semiconductor device. The conductive layer may be a silicon layer. An example is a semiconductor device. The semiconductor device includes a channel layer, a barrier layer, a gate layer, and a silicon layer. The channel layer is over a semiconductor substrate. The barrier layer is over the channel layer. The gate layer is over the barrier layer. The silicon layer is over and contacts the gate layer.

Abstract: Semiconductor devices with a source contact extending into a substrate are described. In one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, and a drain access region, where a heterojunction structure is disposed over the semiconductor substrate. The heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A gate stack is disposed over the barrier layer in the gate region. A source contact in the source region extends into the semiconductor substrate, including a first contact with a 2DEG in the heterojunction structure and a second contact with the semiconductor substrate.

Abstract: A device includes first and second device terminals, a fuse, a first circuit, a first transistor, and a control circuit. The fuse terminal couples to the first device terminal. The first circuit couples to the second fuse terminal. The second fuse terminal has a first voltage. The first transistor has a first control input and first and second current terminals. The first current terminal couples to the second fuse terminal, and the second current terminal couples to the second device terminal. The control circuit: turns “on” the first transistor into a saturation region if the first voltage exceeds a threshold and a current through the fuse exceeds a trip threshold current of the fuse; and turns “on” the first transistor into a linear region if the first voltage exceeds a threshold and a current through the fuse is below the trip threshold current of the fuse.

Abstract: The present disclosure generally relates to a semiconductor device that includes a gate electrical contact that forms junctions with different energy barrier heights to a gate layer. In an example, a semiconductor device includes a semiconductor substrate, a drain electrical contact, a source electrical contact, a barrier layer, a gate layer, and a gate electrical contact. The drain and source electrical contacts are on the semiconductor substrate. The barrier layer is over a channel region of the semiconductor substrate between the drain and source electrical contacts. The gate layer is over the barrier layer. The gate layer includes first and second semiconductor portions. The gate electrical contact contacts the gate layer. The gate electrical contact includes first and second metal portions. The first and second metal portions form first and second junctions with the first and second semiconductor portions, respectively. The first and second junctions have different energy barrier heights.

Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.

Abstract: A device includes first and second device terminals, a fuse, a first circuit, a first transistor, and a control circuit. The fuse terminal couples to the first device terminal. The first circuit couples to the second fuse terminal. The second fuse terminal has a first voltage. The first transistor has a first control input and first and second current terminals. The first current terminal couples to the second fuse terminal, and the second current terminal couples to the second device terminal. The control circuit: turns “on” the first transistor into a saturation region if the first voltage exceeds a threshold and a current through the fuse exceeds a trip threshold current of the fuse; and turns “on” the first transistor into a linear region if the first voltage exceeds a threshold and a current through the fuse is below the trip threshold current of the fuse.

Abstract: The present disclosure generally relates to integrated devices with a conductive barrier structure. In an example, a semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, a gate, and a conductive structure. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is of a second semiconductor material and is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The gate is over the barrier layer opposing the channel layer. The conductive structure is electrically coupled between the conductive barrier structure, the channel layer, and the barrier layer.

Abstract: The present disclosure generally relates to integrated devices with a conductive barrier structure. In an example, a semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, a gate, and a conductive structure. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is of a second semiconductor material and is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The gate is over the barrier layer opposing the channel layer. The conductive structure is electrically coupled between the conductive barrier structure, the channel layer, and the barrier layer.

Abstract: A method comprises: forming a first metallization layer on a semiconductor die, the first metallization layer including a metal fuse; and forming a second metallization layer on the first metallization layer, in which the second metallization layer includes a thermal conductor spaced from the metal fuse, and the first metallization layer is between the second metallization layer and the semiconductor die.