Abstract: A data processing system which includes an address bus connected to k computer elements is supervised with the aid of an arrangement including a plurality of indication registers connected to the bus and to an error signal generator. The address bus is capable of transferring 2n>k binary addresses. The indication registers are each accessed by its address transferred through the bus and each register stores an indication if its address is also assigned one of the computer elements. The generator generates an error signal on the reception of an indication that an address being transferred through the bus is not assigned a computer element.