Abstract: A flipflop having a clock input for applying a clock signal, a data input for applying a data signal, a noninverting output and an inverting output, where the flipflop has a first holding element with a first feedback loop and a second holding element with a second feedback loop, where the first and second feedback loops each have a first node and a second node, where the first holding element is designed such that upon a first clock edge of the clock signal the logic value of the data signal is transferred to the first holding element and the logic value of the data signal is made available on the first node in the first feedback loop, where the first node in the first feedback loop is coupled to the first node in the second feedback loop in order to transfer the signal value which is on the first node in the first feedback loop to the second holding element upon a second clock edge of the clock signal and to output the signal value on the noninverting output, wherein the second node in the first feedback lo

Abstract: A flip-flop includes a clock signal input, a data signal input, non-inverting and inverting outputs, a data acceptance unit, and a storage unit having a feedback loop with first and second inverter circuits having feedback to one another. The inverting output is coupled to the first inverter circuit output and the non-inverting output is coupled to the second inverter circuit output. The acceptance unit, dependent upon the data and clock signals present, allocates a programming potential to the first or the second inverter circuit input and applies no potential to the respective other input of the circuits. The acceptance unit has a first switching element applying the predetermined programming potential to the input of the first inverter circuit dependent upon the clock and data signals and a second switching element applying the predetermined programming potential to the second inverter circuit input dependent upon the clock and data signals.

Abstract: A flipflop having a clock input for applying a clock signal, a data input for applying a data signal, a noninverting output and an inverting output, where the flipflop has a first holding element with a first feedback loop and a second holding element with a second feedback loop, where the first and second feedback loops each have a first node and a second node, where the first holding element is designed such that upon a first clock edge of the clock signal the logic value of the data signal is transferred to the first holding element and the logic value of the data signal is made available on the first node in the first feedback loop, where the first node in the first feedback loop is coupled to the first node in the second feedback loop in order to transfer the signal value which is on the first node in the first feedback loop to the second holding element upon a second clock edge of the clock signal and to output the signal value on the noninverting output, wherein the second node in the first feedback lo

Abstract: A flip-flop includes a clock signal input, a data signal input, non-inverting and inverting outputs, a data acceptance unit, and a storage unit having a feedback loop with first and second inverter circuits having feedback to one another. The non-inverting output is coupled to the first inverter circuit output and the inverting output is coupled to the second inverter circuit output. The acceptance unit, dependent upon the data and clock signals present, allocates a programming potential to the first or the second inverter circuit input and applies no potential to the respective other input of the circuits. The acceptance unit has a first switching element applying the predetermined programming potential to the input of the first inverter circuit dependent upon the clock and data signals and a second switching element applying the predetermined programming potential to the second inverter circuit input dependent upon the clock and data signals.

Abstract: A flip-flop circuit comprises a master latch circuit (2), which receives an input signal (D), and, connected in series therewith, a slave latch circuit (3), the two latch circuits (2, 3) being actuated complementarily-to one another by a clock signal. The output signal value (Q,{overscore (Q)}) of the flip-flop circuit is emitted from the output of the slave latch circuit (3) not directly but via a non-differential output driver circuit (4), e.g. an inverter circuit.